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Dual-modulus prescaler

About: Dual-modulus prescaler is a(n) research topic. Over the lifetime, 539 publication(s) have been published within this topic receiving 6238 citation(s).

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Papers
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Journal ArticleDOI: 10.1109/4.735547
Jan Craninckx1, Michiel Steyaert1Institutions (1)
01 Jan 1998-
Abstract: A prototype frequency synthesizer for the DCS-1800 system has been integrated in a standard 0.4 /spl mu/m CMOS process without any external components. A completely monolithic design has been made feasible by using an optimized hollow-coil inductor low-phase-noise voltage-controlled oscillator (VCO). The frequency divider is an eight-modulus phase-switching prescaler that achieves the same speed as asynchronous dividers. The die area was minimized by using a dual-path active loop filter. An indirect linearization technique was implemented for the VCO gain. The resulting architecture is a fourth-order, type-2 charge-pump phase-locked loop. The measured settling time is 300 /spl mu/s, and the phase noise is up to -123 dBc/Hz at 600 kHz and -138 dBc/Hz at 3 MHz offset.

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Topics: Dual-modulus prescaler (63%), Frequency divider (62%), Frequency synthesizer (62%) ...read more

288 Citations


Journal ArticleDOI: 10.1109/4.508200
Jan Craninckx1, Michiel Steyaert1Institutions (1)
Abstract: A dual-modulus divide-by-128/129 prescaler has been developed in a 0.7-/spl mu/m CMOS technology. A new circuit technique enables the limitation of the high-speed section of the prescaler to only one divide-by-two flipflop. In that way, a dual-modulus prescaler with the same speed as an asynchronous divider can be obtained. The measured maximum input frequency of the prescaler is up to 2.65 GHz at 5 V power supply voltage. Running at a power supply of 3 V, the circuit consumes 8 mA at a minimum input frequency of 1.75 GHz.

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282 Citations


Journal ArticleDOI: 10.1109/4.482195
Jan Craninckx1, Michiel Steyaert1Institutions (1)
Abstract: The implementation of the two high-frequency building blocks for a low-phase-noise 1.8-GHz frequency-synthesizing PLL in a standard 0.7-/spl mu/m CMOS process is discussed. The VCO uses on-chip bondwires, instead of spiral inductors, for low noise and low power. The design of these bondwire inductors is discussed in great detail. A general formula for the theoretical limit of the phase noise of LC-tuned oscillators is presented. The design of a special LC-tank allows a trade-off between noise and power. The realized VCO has a phase noise of -115 dBc/Hz at 200 kHz from the 1.8-GHz carrier and consumes 8 mA from a 3-V supply. The prescaler has a fixed division ratio of 128 and uses an enhanced ECL-alike high-frequency D-flipflop. Its power consumption is 28 mW.

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Topics: Dual-modulus prescaler (63%), Phase noise (63%), Voltage-controlled oscillator (59%) ...read more

253 Citations


Journal ArticleDOI: 10.1109/19.87022
B. Miller1, R.J. Conley1Institutions (1)
Abstract: Fractional-N frequency synthesis using a phase locked loop (PLL) is considered. Advances in oversampling A/D conversion technology are incorporated into fractional-N synthesis, allowing the spectrum of error energy to be shaped so that fractional synthesis error energy is pushed away from the carrier. Based on this new technology, a CMOS integrated fractional-N divider was successfully developed. A complete fractional-N PLL was constructed utilizing only a CMOS divider, a dual modulus prescaler, a simple loop filter, and a voltage controlled oscillator (VCO). The resulting PLL exhibits no fractional spurs. >

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Topics: Frequency divider (67%), Current divider (61%), Dual-modulus prescaler (58%) ...read more

233 Citations


Proceedings ArticleDOI: 10.1109/FREQ.1990.177545
B. Miller1, B. Conley1Institutions (1)
23 May 1990-
Abstract: Based on oversampling A/D conversion technology which allows the spectrum of error energy to be shaped so that fractional synthesis error energy is pushed away from the carrier, a CMOS integrated fractional-N divider is presented. A complete fractional-N phase locked loop (PLL) which was constructed utilizing only the CMOS divider, a dual modulus prescaler, a simple loop filter, and a voltage controlled oscillator is discussed. The resulting PLL is shown to exhibit no fractional spurs. >

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Topics: Frequency divider (67%), Current divider (63%), Dual-modulus prescaler (58%) ...read more

195 Citations


Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20212
20202
20193
20184
20176
201610

Top Attributes

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Topic's top 5 most impactful authors

Ching-Yuan Yang

10 papers, 183 citations

Shen-Iuan Liu

8 papers, 174 citations

Xiaopeng Yu

8 papers, 128 citations

R. Ahola

7 papers, 23 citations

W.A.M. Van Noije

6 papers, 176 citations

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