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Dynamic frequency scaling

About: Dynamic frequency scaling is a research topic. Over the lifetime, 307 publications have been published within this topic receiving 3567 citations. The topic is also known as: throttling & CPU throttling.


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Proceedings ArticleDOI
07 Oct 2004
TL;DR: This paper proposes heat-and-run SMT thread assignment to increase processor-resource utilization before cooling becomes necessary by co-scheduling threads that use complimentary resources and heat- and-run CMP thread migration to migrate threads away from overheated cores and assign them to free SMT contexts on alternate cores.
Abstract: Power density in high-performance processors continues to increase with technology generations as scaling of current, clock speed, and device density outpaces the downscaling of supply voltage and thermal ability of packages to dissipate heat. Power density is characterized by localized chip hot spots that can reach critical temperatures and cause failure. Previous architectural approaches to power density have used global clock gating, fetch toggling, dynamic frequency scaling, or resource duplication to either prevent heating or relieve overheated resources in a superscalar processor. Previous approaches also evaluate design technologies where power density is not a major problem and most applications do not overheat the processor. Future processors, however, are likely to be chip multiprocessors (CMPs) with simultaneously-multithreaded (SMT) cores. SMT CMPs pose unique challenges and opportunities for power density. SMT and CMP increase throughput and thus on-chip heat, but also provide natural granularities for managing power-density. This paper is the first work to leverage SMT and CMP to address power density. We propose heat-and-run SMT thread assignment to increase processor-resource utilization before cooling becomes necessary by co-scheduling threads that use complimentary resources. We propose heat-and-run CMP thread migration to migrate threads away from overheated cores and assign them to free SMT contexts on alternate cores, leveraging availability of SMT contexts on alternate CMP cores to maintain throughput while allowing overheated cores to cool. We show that our proposal has an average of 9% and up to 34% higher throughput than a previous superscalar technique running the same number of threads.

335 citations

Journal ArticleDOI
TL;DR: In this paper, a PowerPC system-on-a-chip processor which makes use of dynamic voltage scaling and on-the-fly frequency scaling to adapt to the dynamically changing performance demands and power consumption constraints of high-content, battery powered applications is described.
Abstract: A PowerPC system-on-a-chip processor which makes use of dynamic voltage scaling and on-the-fly frequency scaling to adapt to the dynamically changing performance demands and power consumption constraints of high-content, battery powered applications is described. The PowerPC core and caches achieve frequencies as high as 380 MHz at a supply of 1.8 V and active power consumption as low as 53 mW at a supply of 1.0 V. The system executes up to 500 MIPS and can achieve standby power as low as 54 /spl mu/W. Logic supply changes as fast as 10 mV//spl mu/s are supported. A low-voltage PLL supplied by an on-chip regulator, which isolates the clock generator from the variable logic supply, allows the SOC to operate continuously while the logic supply voltage is modified. Hardware accelerators for speech recognition, instruction-stream decompression and cryptography are included in the SOC. The SOC occupies 36 mm/sup 2/ in a 0.18 /spl mu/m, 1.8 V nominal supply, bulk CMOS process.

258 citations

Proceedings ArticleDOI
Kai Ma1, Xue Li2, Wei Chen1, Chi Zhang2, Xiaorui Wang1 
10 Sep 2012
TL;DR: This paper proposes Green GPU, a holistic energy management framework for GPU-CPU heterogeneous architectures that dynamically throttles the frequencies of GPU cores and memory in a coordinated manner, based on their utilizations, for maximized energy savings with only marginal performance degradation.
Abstract: In recent years, GPU-CPU heterogeneous architectures have been increasingly adopted in high performance computing, because of their capabilities of providing high computational throughput. However, the energy consumption is a major concern due to the large scale of such kind of systems. There are a few existing efforts that try to lower the energy consumption of GPU-CPU architectures, but they address either GPU or CPU in an isolated manner and thus cannot achieve maximized energy savings. In this paper, we propose Green GPU, a holistic energy management framework for GPU-CPU heterogeneous architectures. Our solution features a two-tier design. In the first tier, Green GPU dynamically splits and distributes workloads to GPU and CPU based on the workload characteristics, such that both sides can finish approximately at the same time. As a result, the energy wasted on idling and waiting for the slower side to finish is minimized. In the second tier, Green GPU dynamically throttles the frequencies of GPU cores and memory in a coordinated manner, based on their utilizations, for maximized energy savings with only marginal performance degradation. Likewise, the frequency and voltage of the CPU are scaled similarly. We implement Green GPU using the CUDA framework on a real physical test bed with Nvidia GeForce GPUs and AMD Phenom II CPUs. Experiment results show that Green GPU achieves 21.04% average energy savings and outperforms several well-designed baselines.

128 citations

Journal ArticleDOI
TL;DR: A comprehensive assessment of state-of-the-art of dynamic power management (DPM) in wireless sensor networks is provided and aspects of power dissipation in a node are investigated and the strength and limitations of selective switching, dynamic frequency, and voltage scaling are analyzed.
Abstract: In the last few years, interest in wireless sensor networks has increased considerably. These networks can be useful for a large number of applications, including habitat monitoring, structural health monitoring, pipeline monitoring, transportation, precision agriculture, supply chain management, and many more. Typically, a wireless sensor network consists of a large number of simple nodes which operate with exhaustible batteries, unattended. Manual replacement or recharging the batteries is not an easy or desirable task. Hence, how energy is utilized by the various hardware subsystems of individual nodes directly affects the scope and usefulness of the entire network. This paper provides a comprehensive assessment of state-of-the-art of dynamic power management (DPM) in wireless sensor networks. It investigates aspects of power dissipation in a node and analyses the strength and limitations of selective switching, dynamic frequency, and voltage scaling.

128 citations

Journal ArticleDOI
TL;DR: This paper derives simple, yet fundamental formulas to describe the interplay between parallelism of an application, program performance, and energy consumption and derives optimal frequencies allocated to the serial and parallel regions in an application to either minimize the total energy consumption or minimize the energy-delay product.
Abstract: This paper derives simple, yet fundamental formulas to describe the interplay between parallelism of an application, program performance, and energy consumption. Given the ratio of serial and parallel portions in an application and the number of processors, we derive optimal frequencies allocated to the serial and parallel regions in an application to either minimize the total energy consumption or minimize the energy-delay product. The impact of static power is revealed by considering the ratio between static and dynamic power and quantifying the advantages of adding to the architecture capability to turn off individual processors and save static energy. We further determine the conditions under which one can obtain both energy and speed improvement, as well as the amount of improvement. While the formulas we obtain use simplifying assumptions, they provide valuable theoretical insights into energy-aware processor resource management. Our results form a basis for several interesting research directions in the area of energy-aware multicore processor architectures.

114 citations

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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20219
202017
201911
201816
201714
201625