Topic
Dynamic range
About: Dynamic range is a research topic. Over the lifetime, 7576 publications have been published within this topic receiving 101739 citations. The topic is also known as: DNR & DR.
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TL;DR: A high dynamic range CMOS image sensor providing a user-programmable power responsivity curve is presented, besides a 4T active pixel structure, a voltage comparator and an analog memory to implement a time-to-saturation scheme while also providing the standard integrated photo-current signal.
Abstract: A high dynamic range CMOS image sensor providing a user-programmable power responsivity curve is presented. Each pixel integrates, besides a 4T active pixel structure, a voltage comparator and an analog memory to implement a time-to-saturation scheme while also providing the standard integrated photo-current signal. The sensor generates two 10-bit analog outputs allowing a typical dynamic range exceeding 120 dB with a temporal noise lower than 0.13% and a fixed pattern noise of 0.4% (1.7%) of the total signal swing (2 V) at low (high) irradiance without any external calibration procedures. A 140 times 140-pixel array has been fabricated in a 0.35-mum, two-poly four-metal (2P4M), 3.3-V standard CMOS technology. The chip measures 3.9 times 4.6 mm2 with a pixel pitch of 15 mum and a fill factor of 20%.
43 citations
Patent•
28 Apr 1995TL;DR: In this article, an adaptive dynamic range control circuit architecture for an IR-FPA (10) was proposed to achieve a higher dynamic range. But, the circuit architecture required fewer bits to resolve the useable signal information and dynamic range, and it required an adaptive feedback circuitry to suppress the charge pedestal.
Abstract: An adaptive dynamic range control circuit architecture is disclosed that enables an IR-FPA (10) to achieve a higher dynamic range. The circuit architecture significantly reduces a resolution required for an analog-to-digital converter (ADC 24) that converts the analog output signals of the IR-FPA to a digital representation. In a preferred embodiment of this invention a column CTIA readout integrated circuit architecture is used in conjunction with the adaptive feedback circuitry of this invention to provide pedestal suppression on a per-pixel basis for the IR-FPA. The use of the circuitry of this invention modifies the conventional column CTIA amplifier configuration to a configuration having an auto-zeroed charge ratioed gain stage (50). One advantage to this technique is that by suppressing the charge pedestal, the usable signal output from the IR-FPA can be brought off-chip to the readout integrated circuit at a much higher gain. As a result, the ADC requires fewer bits to resolve the useable signal information and dynamic range.
43 citations
TL;DR: The addition of a fast loop outside the flash ADC can break this limit and compensate for one and half clock cycles of delay at the cost of reducing the order of noise shaping by one, resulting in a lowpass continuous-time ΔΣ ADC with the highest reported sampling rate in a 0.18 m process.
Abstract: The maximum sampling rate of a continuous-time ΔΣ modulator in a given process is limited by the minimum flash ADC delay that can be realized. Excess loop delay compensation techniques that are widely used can compensate for delays up to half a clock cycle. Addition of a fast loop outside the flash ADC can break this limit and compensate for one and half clock cycles of delay at the cost of reducing the order of noise shaping by one. This technique, along with a low latency flash ADC, and a delay free calibrated DAC, result in a lowpass continuous-time ΔΣ ADC with the highest reported sampling rate in a 0.18 m process. The prototype occupies 0.68 mm2 , consumes 47.6 mW, and operates at 800 MS/s. In a 16 MHz bandwidth (oversampling ratio of 25), the dynamic range, maximum signal to noise ratio, and maximum signal to noise and distortion ratios are 75 dB, 67 dB, and 65 dB respectively. In a 32 MHz bandwidth, the dynamic range, maximum signal to noise ratio, and maximum signal to noise and distortion ratios are 64 dB, 57 dB, and 57 dB, respectively.
43 citations
TL;DR: In this paper, an exposed core microstructured optical fiber was used as a Mach-Zehnder and Sagnac interferometer to achieve a detection limit of as low as 6.02 × 10−6 this paper.
Abstract: A refractive index (RI) fiber sensor with low detection limit but large dynamic range is proposed and demonstrated using an exposed core microstructured optical fiber. The exposed-core fiber is highly birefringent due to its asymmetry and also supports multimode propagation; thus, can be used simultaneously as a Mach-Zehnder and Sagnac interferometer. The Mach-Zehnder interference is significantly more phase sensitive to RI due to a longer effective path length difference. This leads to a lower detection limit compared to that for the Sagnac interferometer, which has a larger free spectral range that allows the dynamic range of the RI measurement to be extended. By combining these two interferometers, the proposed sensor achieves a detection limit of as low as 6.02 × 10−6 refractive index units (RIU) while maintaining a large dynamic range from 1.3320 to 1.3465 RIU. The proposed sensor also has the advantages of biocompatibility, low cost, high stability, small size, ability to operate remotely and to be fabricated.
43 citations
TL;DR: An ultralow-voltage and low-power adaptive sigma-delta analog-to-digital converter (SDADC) with a 10-bit dynamic range for bio-microsystem applications is presented and it is revealed that the dynamic range is still over 60 dB without degrading by digital circuits.
Abstract: An ultralow-voltage and low-power adaptive sigma-delta analog-to-digital converter (SDADC) with a 10-bit dynamic range for bio-microsystem applications is presented. The proposed SDADC includes a switched-current sigma-delta modulator (SISDM) and a digital decimator. In order to achieve the low-voltage requirement, a novel class-AB switched-current memory cell is adopted to implement the SISDM with the oversampling ratio (OSR) of 64. In addition, a proposed differential current comparator and a low-voltage 1-bit switched-current digit-to-analog converter (SIDAC) are used for the design of the SDM. Benefits from the SISDM using the class-AB memory cell are low power consumption and high dynamic range. Moreover, a new single-multiplier structure is presented to implement the finite-impulse-response (FIR) digital filters which are the major hardware elements in the decimator. For the various applications with different biosignal frequencies, the SDADC could be manipulated in different operating modes. The overall ADC has been implemented in a TSMC 0.18-mum 1P6M standard CMOS process technology. Without a voltage booster to raise the gate voltage of switches, measurement results show that the SISDM has a dynamic range over 60 dB and a power consumption of 180 muW with an input signal of 1.25-kHz sinusoid wave and 5-kHz bandwidth under a single 0.8-V power supply for electroneurography signals. In addition, the postlayout simulations of SDADC including SISDM and decimator reveal that the dynamic range is still over 60 dB without degrading by digital circuits
43 citations