Dynamic range

About: Dynamic range is a research topic. Over the lifetime, 7576 publications have been published within this topic receiving 101739 citations. The topic is also known as: DNR & DR.

An Evaluation of Ultrasound NDE Correlation Flaw Detection Systems

Abstract: The advantages and limitations of correlation flaw detec- tion systems are studied with a new system which uses a digital delay Line to replace the acoustic delay line of our original random signal flaw detection system. A general signal-to-noise ratio (SNR) formula is derived for correlation systems which includes the effects of clutter, background receiver noise, and self-noise. Experimental studies con- ducted with both m-sequences and random signals, to verify the theo- retical analysis, indicate that in normal operation the correlation system performance is essentially equivalent in resolution and signal-toaoise ratio for these two types of transmit signals. Comparison of the signal- to-noise ratio formulas for pulse-echo and a correlation system suggests that under high input SNR conditions and where high-speed operation is also required, the pulse-echo system provides higher dynamic range and better output signal-tenoise ratio than a correlation system using either of the two types of signals studied. Under all other operating conditions, except when detection is clutter limited, the correlation system is shown to provide superior performance when compared to a conventional pulse-echo system, and can detect echo signals, buried in receiver noise and surrounded by clutter, which a conventional pulse- echo system would be unable to detect.

Progress in Design of Improved High Dynamic Range Analog-to-Digital Converters

Abstract: We describe several improvements that are being pursued to improve the dynamic range of lowpass phase modulation-demodulation (PMD) analog-to-digital converters (ADC). The existing ADC has been tested at sampling frequencies up to 29.44 GHz; a 89.15 dB signal to noise ratio (SNR) is achieved for a 10 MHz sinusoidal input, with the noise being measured in a reference 10 MHz bandwidth in the decimated band. The first improved approach involves a multi-rate ADC where the modulator sampling frequency is increased in multiples of the decimation filter clock. We have tested the multi-rate ADCs at sampling frequencies up to 46.08 GHz and 29.44 GHz for chips fabricated using the 4.5 and 1 kA/cm2 fabrication processes respectively. For a single channel ADC, with a 9.92 MHz sinusoidal input, sampled at 29.44 GHz, the SNR is 83.93 dB in a reference 10 MHz bandwidth. The spur-free dynamic range (SFDR) is 95 dB. In another improved architecture, called the quarter-rate ADC, the modified quantizer quadruples the input dynamic range by distributing the input in a cyclical fashion to four output channels, each operating at a quarter of the fluxon transport rate. This enables quadrupling the synchronizer channels, providing an opportunity for up to 12 dB performance enhancement. A parallel counter following the multi-channel synchronizer converts the differential code to a multi-bit binary code, which is further processed by the decimation filter. A prototype version of this ADC with a two channel synchronizer, fabricated using the 4.5 kA/cm2 process, has been tested up to a sampling frequency of 25.6 GHz. For a 10 MHz sinusoidal input, the SNR is 82.54 dB, with the noise measured in a reference 10 MHz bandwidth. We are also designing a subranging ADC with two PMD front-ends. Simulation results promise greater than 20 dB performance enhancement.

Improved Digital-to-Analog Conversion Using Multi-Electrode Mach–Zehnder Interferometer

Abstract: An improved version of a digital-to-analog converter (DAC) based on a multi-electrode Mach-Zehnder interferometer (MZI) is presented and analyzed. The device described has superior performance regarding both linearity and dynamic range. The improvements are achieved by utilizing a special mapping method between the analog input and the digital sequence applied to the device, and by an optimized sectioning method for the electrodes. Further improvement in linearity is attained by allowing the number of electrodes M to be larger than the number of digitization bits N (M > N). An analytical and systematic method for performing the mapping and selecting the electrodes' sizes is explicitly described and shown to be optimal. A comparison of the proposed approach to previously reported biased MZI reveals that dynamic range and linearity are significantly improved which is translated to increased resolution and reduced quantization errors. It follows from the optimization process that quantization and nonlinearity errors can be reduced to any extent by appropriately increasing the number of electrodes.

A 15-b pipelined CMOS floating-point A/D converter

Abstract: A floating-point approach can be used to extend the dynamic range of analog-to-digital (A/D) converters in applications where large signals need not be encoded with a precision greater than that required for small signals. Owing to the nonuniform nature of the quantization in a floating-point A/D converter (FADC), it is possible to sacrifice a large peak signal-to-noise ratio to obtain savings in power dissipation and area while achieving a large dynamic range. A 15-b switched-capacitor pipelined FADC has been designed with a 10-b mantissa and an exponent that provides an additional 5 bits of dynamic range. The increased dynamic range is obtained with a three-stage pipelined variable gain amplifier, while the mantissa is determined by a uniform 10-b pipelined A/D converter. An experimental prototype of the converter has been integrated in a 0.5 /spl mu/m CMOS technology. It achieves a dynamic range of 90 dB at a conversion rate of 20 MSamples/s with a total power dissipation of 380 mW.

A Low-Power, Compact, Adaptive Logarithmic Transimpedance Amplifier Operating Over Seven Decades of Current

Abstract: This paper presents a detailed insight into the design space of wide-range transimpedance amplifiers enabling the design of micro-power, adaptive circuits for integrated current sensing applications. The analysis proves that the power dissipation of the nonadaptive structures varies linearly with dynamic range and quadratically with bandwidth. We present two adaptation techniques, modifying the bias current or output resistance, both of which alleviate this strong dependence on dynamic range. It is shown that adapting the bias current is most suitable for our application which requires a modest bandwidth but very wide dynamic range. Measurements demonstrate operation with currents ranging seven orders of magnitude from 200 fA to 2 muA with an average error of 0.8% and maximum error of 3.4%. The power consumption averaged over this entire range of currents is 3.45 muW . Either signal-to-noise ratio (SNR) or bandwidth can be made to tradeoff with the input current magnitude depending on the application. If the bandwidth is limited to 5 kHz, it achieves an average SNR of 65 dB.