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Dynamic range

About: Dynamic range is a research topic. Over the lifetime, 7576 publications have been published within this topic receiving 101739 citations. The topic is also known as: DNR & DR.


Papers
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Journal ArticleDOI
TL;DR: In this article, a phase generated carrier is used to detect phase shifts in the microradian range, which obviates the phase tracker resetting problem encountered in active homodyne detection schemes.
Abstract: A method of homodyne demodulation using a phase generated carrier is described and experimentally demonstrated. The method has a large dynamic range, good linearity, and is capable of detecting phase shifts in the microradian range. The detection scheme obviates the phase tracker resetting problem encountered in active homodyne detection schemes. Two methods of producing the carrier are presented, one employing a piezoelectric stretcher, the other using current induced frequency modulation of the diode laser source. These two methods are compared. The origins of the noise limiting the system are briefly discussed.

403 citations

Journal ArticleDOI
TL;DR: It is demonstrated that in this mode the FReLoN can be applied equally to the investigation of rapid changes in long range order and local order and in situations of x-ray hardness and flux beyond the capacity of other detectors.
Abstract: Originally conceived and developed at the European Synchrotron Radiation Facility (ESRF) as an "area" detector for rapid x-ray imaging studies, the fast readout low noise (FReLoN) detector of the ESRF [J.-C. Labiche, ESRF Newsletter 25, 41 (1996)] has been demonstrated to be a highly versatile and unique detector. Charge coupled device (CCD) cameras at present available on the public market offer either a high dynamic range or a high readout speed. A compromise between signal dynamic range and readout speed is always sought. The parameters of the commercial cameras can sometimes be tuned, in order to better fulfill the needs of specific experiments, but in general these cameras have a poor duty cycle (i.e., the signal integration time is much smaller than the readout time). In order to address scientific problems such as time resolved experiments at the ESRF, a FReLoN camera has been developed by the Instrument Support Group at ESRF. This camera is a low noise CCD camera that combines high dynamic range, high readout speed, accuracy, and improved duty cycle in a single image. In this paper, we show its application in a quasi-one-dimensional sense to dynamic problems in materials science, catalysis, and chemistry that require data acquisition on a time scale of milliseconds or a few tens of milliseconds. It is demonstrated that in this mode the FReLoN can be applied equally to the investigation of rapid changes in long range order (via diffraction) and local order (via energy dispersive extended x-ray absorption fine structure) and in situations of x-ray hardness and flux beyond the capacity of other detectors.

391 citations

Journal ArticleDOI
TL;DR: In this article, a generalized notion of superposition has been used for nonlinear filtering of signals which can be expressed as products or as convolutions of components in audio dynamic range compression and expansion, image enhancement with applications to bandwidth reduction, echo removal, and speech waveform processing.
Abstract: An approach to some nonlinear filtering problems through a generalized notion of superposition has proven useful In this paper this approach is investigated for the nonlinear filtering of signals which can be expressed as products or as convolutions of components. The applications of this approach in audio dynamic range compression and expansion, image enhancement with applications to bandwidth reduction, echo removal, and speech waveform processing are presented.

383 citations

Journal ArticleDOI
TL;DR: In this paper, a 352/spl times/288 pixel CMOS image sensor chip with per-pixel single-slope ADC and dynamic memory in a standard digital 0.18-/spl mu/m CMOS process is described.
Abstract: A 352/spl times/288 pixel CMOS image sensor chip with per-pixel single-slope ADC and dynamic memory in a standard digital 0.18-/spl mu/m CMOS process is described. The chip performs "snapshot" image acquisition, parallel 8-bit A/D conversion, and digital readout at continuous rate of 10000 frames/s or 1 Gpixels/s with power consumption of 50 mW. Each pixel consists of a photogate circuit, a three-stage comparator, and an 8-bit 3T dynamic memory comprising a total of 37 transistors in 9.4/spl times/9.4 /spl mu/m with a fill factor of 15%. The photogate quantum efficiency is 13.6%, and the sensor conversion gain is 13.1 /spl mu/V/e/sup -/. At 1000 frames/s, measured integral nonlinearity is 0.22% over a 1-V range, rms temporal noise with digital CDS is 0.15%, and rms FPN with digital CDS is 0.027%. When operated at low frame rates, on-chip power management circuits permit complete powerdown between each frame conversion and readout. The digitized pixel data is read out over a 64-bit (8-pixel) wide bus operating at 167 MHz, i.e., over 1.33 GB/s. The chip is suitable for general high-speed imaging applications as well as for the implementation of several still and standard video rate applications that benefit from high-speed capture, such as dynamic range enhancement, motion estimation and compensation, and image stabilization.

382 citations

Journal ArticleDOI
05 Feb 1998
TL;DR: A 256x256 CMOS active pixel sensor (APS) is described for an automotive stereo-vision system that simultaneously provides flexibility, user-adjustability, and digital control, with no reduction of fill factor.
Abstract: A 256x256 CMOS active pixel sensor (APS) is described for an automotive stereo-vision system. Illumination may vary over several orders of magnitude, requiring a high dynamic range imager. Dynamic range is increased 20/spl times/ using a special clocking scheme for the lateral overflow gate. This dynamic range enhancement offers improvements over previously-described techniques. It simultaneously provides flexibility, user-adjustability, and digital control, with no reduction of fill factor. On-chip column-parallel cyclic analog-to-digital converters (ADCs) produce digital output at frame rates from 30 to 390 frames/s.

371 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023176
2022383
2021189
2020265
2019325
2018334