eDRAM

About: eDRAM is a research topic. Over the lifetime, 416 publications have been published within this topic receiving 7782 citations. The topic is also known as: embedded DRAM & embedded dynamic random-access memory.

An energy-efficient and scalable eDRAM-based register file architecture for GPGPU

Abstract: The heavily-threaded data processing demands of streaming multiprocessors (SM) in a GPGPU require a large register file (RF). The fast increasing size of the RF makes the area cost and power consumption unaffordable for traditional SRAM designs in the future technologies. In this paper, we propose to use embedded-DRAM (eDRAM) as an alternative in future GPGPUs. Compared with SRAM, eDRAM provides higher density and lower leakage power. However, the limited data retention time in eDRAM poses new challenges. Periodic refresh operations are needed to maintain data integrity. This is exacerbated with the scaling of eDRAM density, process variations and temperature. Unlike conventional CPUs which make use of multi-ported RF, most of the RFs in modern GPGPU are heavily banked but not multi-ported to reduce the hardware cost. This provides a unique opportunity to hide the refresh overhead. We propose two different eDRAM implementations based on 3T1D and 1T1C memory cells. To mitigate the impact of periodic refresh, we propose two novel refresh solutions using bank bubble and bank walk-through. Plus, for the 1T1C RF, we design an interleaved bank organization together with an intelligent warp scheduling strategy to reduce the impact of the destructive reads. The analysis shows that our schemes present better energy efficiency, scalability and variation tolerance than traditional SRAM-based designs.

Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules

Abstract: EDRAM cells require periodic refresh, which ends up consuming substantial energy for large last-level caches. In practice, it is well known that different eDRAM cells can exhibit very different charge-retention properties. Unfortunately, current systems pessimistically assume worst-case retention times, and end up refreshing all the cells at a conservatively-high rate. In this paper, we propose an alternative approach. We use known facts about the factors that determine the retention properties of cells to build a new model of eDRAM retention times. The model is called Mosaic. The model shows that the retention times of cells in large eDRAM modules exhibit spatial correlation. Therefore, we logically divide the eDRAM module into regions or tiles, profile the retention properties of each tile, and program their refresh requirements in small counters in the cache controller. With this architecture, also called Mosaic, we refresh each tile at a different rate. The result is a 20x reduction in the number of refreshes in large eDRAM modules — practically eliminating refresh as a source of energy consumption.

Advanced Semiconductor Memories: Architectures, Designs, and Applications

Abstract: A valuable reference for the most vital microelectronic components in the marketplace DRAMs are the technology drivers of high volume semiconductor fabrication processes for new generation products that, in addition to computer markets, are finding increased usage in automotive, aviation, military and space, telecommunications, and wireless industries. A new generation of high-density and high-performance memory architectures evolving for mass storage devices, including embedded memories and nonvolatile flash memories, are serving a diverse range of applications. Comprehensive and up to date, Advanced Semiconductor Memories: Architectures, Designs, and Applications offers professionals in the semiconductor and related industries an in-depth review of advanced semiconductor memories technology developments. It provides details on: Static Random Access Memory technologies including advanced architectures, low voltage SRAMs, fast SRAMs, SOI SRAMs, and specialty SRAMs (multiport, FIFOs, CAMs) High Performance Dynamic Random Access Memory-DDRs, synchronous DRAM/SGRAM features and architectures, EDRAM, CDRAM, Gigabit DRAM scaling issues and architectures, multilevel storage DRAMs, and SOI DRAMs Applications-specific DRAM architectures and designs - VRAMs, DDR SGRAMs, RDRAMs, SLDRAMs, 3-D RAM Advanced Nonvolatile Memory designs and technologies, including floating gate cell theory, EEPROM/flash memory cell design, and multilevel flash FRAMs and reliability issues Embedded memory designs and applications, including cache, merged processor, DRAM architectures, memory cards, and multimedia applications Future memory directions with megabytes to terabytes storage capacities using RTDs, single electron memories, etc. A continuation of the topics introduced in Semiconductor Memories: Technology, Testing, and Reliability, the author's earlier work, Advanced Semiconductor Memories: Architectures, Designs, and Applications offers a much-needed reference to the major developments and future directions of advanced semiconductor memory technology.

On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators

Abstract: Deep neural network (DNN) inference tasks have become ubiquitous workloads on mobile SoCs and demand energy-efficient hardware accelerators. Mobile DNN accelerators are heavily area-constrained, with only minimal on-chip SRAM, which results in heavy use of inefficient off-chip DRAM. With diminishing returns from conventional silicon technology scaling, emerging memory technologies that offer better area density than SRAM can boost accelerator efficiency by minimizing costly off-chip DRAM accesses. This paper presents a detailed design space exploration (DSE) of technology-system co-design for systolic-array accelerators. We focus on practical/mature on-chip memory technologies, including SRAM, eDRAM, MRAM, and 3D vertical RRAM (VRRAM). The DSE employs state-of-the-art optimizations (e.g., model compression and optimized buffer scheduling), and evaluates results on important models including ResNet-50, MobileNet, and Faster-RCNN. Compared to an SRAM/DRAM baseline, MRAM-based accelerators show up to 4.68× energy benefits (57% area overhead), while a 3D VRRAM-based design achieves 2.22 × energy benefits (33% area reduction).

RANA: towards efficient neural acceleration with refresh-optimized embedded DRAM

Abstract: The growing size of convolutional neural networks (CNNs) requires large amounts of on-chip storage. In many CNN accelerators, their limited on-chip memory capacity causes massive off-chip memory access and leads to very high system energy consumption. Embedded DRAM (eDRAM), with higher density than SRAM, can be used to improve on-chip buffer capacity and reduce off-chip access. However, eDRAM requires periodic refresh to maintain data retention, which costs much energy consumption. Refresh is unnecessary if the data's lifetime in eDRAM is shorter than the eDRAM's retention time. Based on this principle, we propose a Retention-Aware Neural Acceleration (RANA) framework for CNN accelerators to save total system energy consumption with refresh-optimized eDRAM. The RANA framework includes three levels of techniques: a retention-aware training method, a hybrid computation pattern and a refresh-optimized eDRAM controller. At the training level, CNN's error resilience is exploited in training to improve eDRAM's tolerable retention time. At the scheduling level, RANA assigns each CNN layer with a computation pattern that consumes the lowest energy. At the architecture level, a refresh-optimized eDRAM controller is proposed to alleviate unnecessary refresh operations. We implement an evaluation platform to verify RANA. Owing to the RANA framework, 99.7% eDRAM refresh operations can be removed with negligible performance and accuracy loss. Compared with the conventional SRAM-based CNN accelerator, an eDRAM-based CNN accelerator strengthened by RANA can save 41.7% off-chip memory access and 66.2% system energy consumption, with the same area cost.