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EEPROM

About: EEPROM is a research topic. Over the lifetime, 5139 publications have been published within this topic receiving 80556 citations. The topic is also known as: electrically erasable programmable ROM & electrically erasable programmable read-only memory.


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Patent
30 Mar 1990
TL;DR: In this paper, the authors proposed selective multiple sector erase, in which any combinations of Flash sectors may be erased together, and select sectors among the selected combination may also be de-selected during the erase operation.
Abstract: A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

1,279 citations

Patent
02 Aug 1998
TL;DR: In this paper, an electrically erasable programmable read-only memory (EEPROM) with a non-conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed.
Abstract: An electrically erasable programmable read only memory (EEPROM) having a non conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the EEPROM device. The non conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. The memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and the source while the drain is grounded. Application of relatively low gate voltages combined with reading in the reverse direction greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region. In addition, the memory cell can be erased by applying suitable erase voltages to the gate and the drain so as to cause electrons to be removed from the charge trapping region of the nitride layer. Similar to programming, a narrower charge trapping region enables much faster erase cycles.

1,195 citations

Patent
15 Oct 1991
TL;DR: In this article, an intelligent erase algorithm is used to prolong the useful life of the memory cells, which is useful as a solid state memory in place of magnetic disk storage devices in computer systems.
Abstract: Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

1,037 citations

Patent
11 Apr 1990
TL;DR: In this article, the read, write and erase of EEprom memory enable nonvolatile multi-state memory to operate with enhanced performance over an extended period of time by using a set of reference cells which closely track and make adjustment for the variations presented by memory cells.
Abstract: Improvements in the circuits and techniques for read, write and erase of EEprom memory enable nonvolatile multi-state memory to operate with enhanced performance over an extended period of time. In the improved circuits for normal read, and read between write or erase for verification, the reading is made relative to a set of threshold levels as provided by a corresponding set of reference cells which closely track and make adjustment for the variations presented by the memory cells. In one embodiment, each Flash sector of memory cells has its own reference cells for reading the cells in the sector, and a set of reference cells also exists for the whole memory chip acting as a master reference. In another embodiment, the reading is made relative to a set of threshold levels simultaneously by means of a one-to-many current mirror circuit. In improved write or erase circuits, verification of the written or erased data is done in parallel on a group of memory cells at a time and a circuit selectively inhibits further write or erase to those cells which have been correctly verified. Other improvements includes programming the ground state after erase, independent and variable power supply for the control gate of EEprom memory cells.

945 citations

Journal ArticleDOI
TL;DR: A novel fully integrated passive transponder IC with 4.5- or 9.25-m reading distance at 500-mW ERP or 4-W EIRP base-station transmit power, operating in the 868/915-MHz ISM band with an antenna gain less than -0.5 dB.
Abstract: This paper presents a novel fully integrated passive transponder IC with 4.5- or 9.25-m reading distance at 500-mW ERP or 4-W EIRP base-station transmit power, respectively, operating in the 868/915-MHz ISM band with an antenna gain less than -0.5 dB. Apart from the printed antenna, there are no external components. The IC is implemented in a 0.5-/spl mu/m digital two-poly two-metal digital CMOS technology with EEPROM and Schottky diodes. The IC's power supply is taken from the energy of the received RF electromagnetic field with help of a Schottky diode voltage multiplier. The IC includes dc power supply generation, phase shift keying backscatter modulator, pulse width modulation demodulator, EEPROM, and logic circuitry including some finite state machines handling the protocol used for wireless write and read access to the IC's EEPROM and for the anticollision procedure. The IC outperforms other reported radio-frequency identification ICs by a factor of three in terms of required receive power level for a given base-station transmit power and tag antenna gain.

875 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20238
202214
202113
202050
201943
201870