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Showing papers on "Effective number of bits published in 1971"


Patent
Hsiao Mu-Yue1, Wadie F. Mikhail1
18 Oct 1971
TL;DR: In this article, a method and apparatus for detecting and correcting double errors automatically by generating syndrome S bits from a binary word having check bits and data bits was provided, and the syndrome S themselves themselves were decoded to locate and correct single errors.
Abstract: A method and apparatus are provided for detecting and correcting double errors automatically by generating syndrome S bits from a binary word having check bits and data bits. The syndrome S bits themselves are decoded to locate and correct single errors. Wen double errors occur in the binary word, the syndrome S bits automatically operate a switching device which changes the bits of the binary word one at a time to correct one of the double errors. If one of the double errors is not corrected when a given bit is changed, this is indicated by the syndrome S bits, and the bit under test is restored as the next bit of the binary word is changed or complemented. Whenever one of the double errors is corrected by the switching device, the syndrome bits then indicate the location of the remaining single error, and the syndrome S bits are decoded to correct the second one of the double errors.

14 citations


Patent
08 Dec 1971
TL;DR: In this article, a bipolar sequential analog-to-digital converter is designed to have two sign bit checks, and when the sign bits do not match, the previously generated bits are corrected before the encoder generates the remaining bits.
Abstract: A bipolar sequential analog-to-digital converter is designed to have two sign bit checks. When the first few encoded bits indicate an input signal near zero, the sign bit is rechecked and the result is compared with the first sign bit detection. When the two are the same, the encoder continues to generate the remaining bits of the code. However, when the sign bits do not match, the previously generated bits are corrected before the encoder generates the remaining bits.

14 citations


Patent
Paul Mecklenburg1
18 Jan 1971
TL;DR: In this article, an approach for error detection and correction in data transmission systems includes a plurality of exclusive-OR circuits and delay registers, and switches responsive to control circuitry selectively apply data bits, as they are generated, to the exclusive OR circuits and delays, which generate a number of partially completed check bits.
Abstract: Apparatus for providing error detection and correction in data transmission systems includes a plurality of exclusive-OR circuits and delay registers. Switches responsive to control circuitry selectively apply data bits, as they are generated, to the exclusive-OR circuits and delay registers which, in turn, generate a number of partially completed check bits. As the check bits are completed in the encoder, they are inserted in the data stream. Check bits similarly generated in a decoder are, compared with the received check bits and the results of this comparison used to locate errors in the data stream. Error correction circuitry then corrects the indicated errors.

9 citations


Patent
26 Jan 1971
TL;DR: In this paper, information stored in a shift register in the form of data bits is serially read out to a logical circuit including gates, pulse stretchers, a storage flip-flop, a NOR gate, and a resistor summer.
Abstract: Information stored in a shift register in the form of data bits is serially read out to a logical circuit including gates, pulse stretchers, a storage flip-flop, a NOR gate, and a resistor summer. The output of the summer is connected to an operational amplifier feeding signals to a wire transmission line or a radio transmitter. The logical circuit is connected such that ''''0'''' data bits appear as zero voltage levels on the transmission line, and ''''1'''' bits appear as +V levels on the line. Space pulses are additionally provided between the data bits as +2V levels on the line, and an end-of-message level of +3V is provided when the last bit is read from the shift register. The voltage levels are maintained during transmission by suitable amplifiers or may be restored at the receiver. The receiver inverts the incoming signals and adds +V. Voltage comparators are fed the resulting signal, and provide outputs for data bits, shift pulses, and endof-message pulses.

8 citations


Patent
22 Dec 1971
TL;DR: In this paper, an error detecting and correcting system for a unit having an essentially subordinate structure, such as a function unit of a computer, is provided for an error detection and correction system.
Abstract: An error detecting and correcting system is provided for a unit having an essentially subordinate structure, such as a function unit of a computer. Correct output signals are assumed for the unit and, accordingly, check bits are formed as a function of the output signals of the unit. These bits are stored with a control word associated with each operation. As the operation is being executed, the check bits are regenerated from the output signals of the function unit and are subsequently compared with the correct check bits previously stored. Non-concurrence of the check bits indicates that an error may have occurred in the unit.

6 citations


Patent
22 Jun 1971
TL;DR: In this article, an improved error correcting coding and decoding system for reliable data transmission was proposed, which can be used either for inversion tolerant decoding and decoding of an appropriate code (such as the (21,11) code) or for noninversion tolerant coding of a related type of code.
Abstract: An improved error correcting coding and decoding system for reliable data transmission. During a first subcycle of decoder operation, estimator logic circuitry generates successive sets of estimator function bits from selected bits of a received code word, and a decision circuit generates successive test bits in accordance with a bit derived from a number of the estimator function bits. A modulo 2 adder compares the successive test bits with the corresponding received bits, and a counter circuit counts the number of disagreements. A disagreement count exceeding a predetermined number indicates that the received code word has become inverted, and circuitry then functions to correct for the inversion by either complementing the received code word before the second decoding subcycle or by complementing the output of the decoding decision circuit during the second subcycle. During the second decoding subcycle, the decision circuit generates successive decoded bits as determined from a majority of the estimator function bits and also from a code word bit if desired. In the event of a "tie" among the estimator bits, the indeterminate majority decision bit is replaced with the corresponding received bit. The encoding and decoding system may be used either for inversion tolerant coding and decoding of an appropriate code (such as the (21,11) code) or for noninversion tolerant coding and decoding of a related type of code (such as the (21,12) code).

5 citations


Patent
25 Jun 1971
TL;DR: In this paper, a system for checking the decoding of an address previously encoded in the form of a group of N bits called input bits is presented. But the system is not suitable for the verification of the identity and/or complementarity of the input and output bits.
Abstract: A system for checking the decoding of an address previously encoded in the form of a group of N bits called input bits. The system performs, on one hand, a re-encoding of such address in the form of N output bits identical to the N input bits, and in the form of their complementary bits N, and, on the other hand, compares the identity and/or complementarity of the input and output bits. The system comprises a first arrangement of 2N relays each having a single contact, a group of n diodes (D1, D2, etc.) per contact, a group of n re-encoding matrices (M1, M2 etc.), a second arrangement of 2N relays each having a contact, and means for comparing the identity and/or the complementarity of the input and output bits.

2 citations


Journal ArticleDOI
TL;DR: The system is analyzed as a data compressor that enhances the source entropy by replacing redundancies by adding an extra bit to each word to signal the substitution.
Abstract: A redundancy replacement system is described. Whenever m bits of an n -bit word are identical with corresponding bits in the preceding word, these bits are replaced by m bits from a second source. An extra bit is added to each word to signal the substitution. If words with m redundant bits occur with probability P(m) , one gains an extra channel of average capacity mP(m) -- 1 . The system is analyzed as a data compressor that enhances the source entropy by replacing redundancies. An effective data compression of 2.11 is obtained for typical voice sources.