Showing papers on "Effective number of bits published in 1972"
Patent•
21 Sep 1972TL;DR: In this paper, the original input bit sequences are broken up into shorter sequences which are cycled in closed loops in a series of shift registers, thereby preserving the original data intact while sampled bits are subjected to preselected Boolean operations.
Abstract: A digital logic display in which a row of light emitting diodes (LED''s) is used to indicate the logic state of each bit of a sequence of bits present at one input. Another row of light emitting diodes is used in one mode to indicate the logic state of each bit of a sequence of bits present at another input, and in another mode to indicate the logic state of each bit of a sequence of bits that result from performing a pre-selected Boolean operation on corresponding bits of the two input sequences. By means of associated digital circuitry, the original input bit sequences are broken up into shorter sequences which are cycled in closed loops in a series of shift registers, thereby preserving the original data intact while sampled bits are subjected to preselected Boolean operations. Also this procedure facilitates the use of a scanning mechanism whereby each output LED is responsive to the logic state of selected bits only periodically.
11 citations
Patent•
21 Apr 1972TL;DR: In this paper, a circuit which treats the characteristic bits and the mantissa bits serially in accordance with a conversion algorithm is presented, where the first term is subtracted from the second term and the difference is used to generate the characteristic bit of the converted signal.
Abstract: Conversion of signals in one compressed segmented PCM code format to a second compressed segmented PCM format is performed directly by means of a circuit which treats the characteristic bits and the mantissa bits serially in accordance with a conversion algorithm. The characteristic bits are applied to a counter circuit whose output is used to produce a first term of the algorithm and the mantissa bits are applied to a shift register whose output is used to generate a second term of the algorithm. The first term is subtracted from the second term and the difference is used to generate the characteristic bits of the converted signal.
5 citations
Patent•
15 Dec 1972
TL;DR: In this paper, a method and apparatus for monitoring the performance of a time division multiplexed transmission system is described, where one part of the signal continues to be transmitted without interruption in the system.
Abstract: A method and apparatus are described for monitoring the performance of a time division multiplexed transmission system. At a test point the time division signal is split. One part of the signal continues to be transmitted without interruption in the system. The other part of the signal is delivered to the apparatus which selectively extracts digital data bits from the time division multiplexed data signal by identifying a group of bits within the data signal after which a sequence of bits, but not all bits, are extracted from the identified group. The remaining bits up through, but not including, the sign bit in a selected digital word are inhibited whereas the sign bit is also extracted. By placing the extracted data bits in positions adjacent in significance to the extracted sign bit, a signal gain is effected upon the digital to analog conversion of the signal. Upon display of the analog signal, transmission characteristics of the system are advantageously obtained by visual analysis.
3 citations