Showing papers on "Effective number of bits published in 1975"

Fast ADC

Abstract: A novel ADC is described, consisting in its simplest and fastest version of a parallel ADC supplying the most significant bits, plus several suitably-connected difference amplifiers in which the input signal undergoes successive folding. Their common output is fed into another parallel ADC which supplies the least significant bits. The conversion rate is of the order of 400 MHz for eight bits. Several versions are described, yielding different trade-offs between speed and the number of discriminators employed.

Circuit arrangement for correcting slip errors in pcm receivers

Abstract: A receiver of n-bit data words, each consisting of k information bits and (n-1) redundancy bits, comprises three error detectors receiving the incoming bit stream in parallel with one another and with a shift register of a transfer circuit, the three error detectors being triggered by timing pulses fed to them in staggered relationship from a clock circuit extracting synchronizing signals from the bit stream. In normal operation, the middle detector generates a recurrent no-error output signal which has no effect upon the cadence of the timing pulses. If either of the two other detectors emits such a no-error output signal in response to a forward or a backward slip by a predetermined number of bits h, the clock circuit is reset to compensate for the slip. The emission of an output signal from any error detector causes the readout of the received bits from the shift register in the transfer circuit.

Apparatus for converting a plurality of signals representative of digital bits of information to an analog signal

Abstract: Apparatus for use in a numerical control system for converting a digitial signal, representing a position of a work piece of material being controlled, to an analog signal for driving a servo motor to correct the position of the work piece. The apparatus includes a circuit for converting a digital signal representing the change in the actual position of the work piece to a plurality of signals representative of digital bits of information representing the error in position of the work piece per unit in time. First and second sets of shift registers for receiving the signals representative of digital bits of information, and at least first and second switches are also provided. Further provided is a circuit for transmitting signals representative of each of the least significant bits of information left within the first and second sets of shift registers, and applying each of the pair of bits of information to respectively control the operation of the first and second switches for predetermined periods of time. The duration of each of the periods of time corresponds to the count of the higher order of the two particular bits which are representative of the signals being transmitted at any particular time. Also provided is an integrator, and a circuit for repetitively applying first and second signals to the integrator at respective magnitudes corresponding to the ratio between the count of each of the two bits represented by the signals being transferred from the respective first and second sets of shift registers at one moment and for a duration controlled by the operation of the first and second switches. An analog signal is thereby obtained from the output of the integrator, which analog signal is equal to the sum of the products of the magnitude of the signals applied to the integrator and the respective predetermined periods of time.

Error syndrome and correction code forming devices

Abstract: In information handling systems, syndrome and correction codes adapted for error signalling and correcting operations are obtained by processing words each made of a definite number of bytes, each byte having a same number of bits and one of the bytes being comprised of the parity incoming bits of the other bytes. An error syndrome and correction code forming device is described which comprises first and second stages of modulo-2 adders (i.e. exclusive-OR circuits), the number of adders in the second stage being equal to the number of bits in the required code, wherein the adders of the first stage form the parity check bits of the bytes and further bits from selective combinations of bits in the word and wherein the bits outputting the adders of the first stage are distributed, together with further bits of the word, to the inputs of the adders of the second stage. Substantially all the adders of the first stage have at least as many inputs as there are information bytes in the word to be processed and substantially all the outputs of said first stage adders are applied to inputs of at least two adders of the second stage.