Showing papers on "Effective number of bits published in 1976"

Error checking and correcting device

Abstract: An error checking and correcting device for providing group error detection in addition to single error correction and double error detection in a codeword transmitted through a modular communication channel is disclosed. The codeword comprises a plurality of data bits and a plurality of check bits. The modular communication channel comprises a plurality of modules in each of which a group (or cluster) of bits are transferred in parallel. In the preferred embodiment, the code word contains 40 bits with 32 data bits and 8 check bits, and the modular communication channel is a computer memory comprising 10 modules with 4 bits per module. At the transmitter, the check bit generator generates the check bits from the data bits in accordance with an H-matrix which is partitioned into h-submatrices corresponding to group boundaries of the memory. The construction of the h-submatrices is in accordance with rules necessary for group error detection in addition to single error correction and double error detection. The check bits are appended to the data bits to form a 40 bit code word which is transmitted through the modular memory. At the receiver, a syndrome bit generator generates 8 syndrome bits from the received code word in accordance with the H-matrix. The output of the syndrome bit generator is coupled to both the error detection circuit and the error location circuit. Should a group in the memory be faulty in the process of transmission resulting in a number of bits in the group being in error, logic means are provided in the error detection circuit to identify correctable good data from uncorrectable bad data. According to the syndrome pattern the error detection circuit permits the utilization of received data if no error is detected, or enables the error location circuit to provide single error correction if a single error is detected; or sets an error flag to prohibit the utilization of received data if a random double error is detected or a plurality of errors in the same group are detected.

System and method for increasing the output data throughput of a computer

Abstract: A circuit and method for increasing the output data per unit time from a computer to its associated peripheral terminals or utilization devices is disclosed in which the computer output address and data lines are time multiplexed by a novel decoding technique which enables the address bits and data bits to be interpreted together to form a new data word having a number of bits equal to the sum of the original data bits and the address bits interpreted as data bits. A plurality of decoders, each at a peripheral terminal and each having an identification address code, enable a window for decoding multiple transfers of data on output address and data lines, said window having a predetermined time duration during which all other peripheral identification address codes are locked out, until the data transfer is completed. A microprocessor embodying the invention is also disclosed in which the output data capability is increased from eight to sixteen bits without hardware modification to the microprocessor.

Digital bit rate converter

Abstract: DIGITAL BIT RATE CONVERTERby Alvin L. Pachynski, Jr. ABSTRACT OF THE DISCLOSURE In a digital communication system, apparatus for upconverting the bit rate, f1, of a digital data source to permit digital transmission at a bit rate f2, where f2 > f1. Pulse stuffing techniques are used to insert a fixed number of time slots in the digital data signal such that the ratio of information time slots to stuffed time slots remains constant.The upconverted signal, consisting of nonredundant data bits and stuffed time slots, is interleaved with framing bits prior to transmission over a digital facility. The framing bits provide the synchronization information to enable the receiver to identify the added time slots and to selectively remove the information data bits from the transmitted line signal. The desired data bits are then restored to their original f1 bit rate.

Apparatus and method for storing parity encoded data from a plurality of input/output sources

Abstract: Apparatus and method are included in the main memory of the data processing system which receives data from a plurality of input/output devices connected to a common bus. During a write cycle of operation, a device applies a plurality of data byte signals together with associated parity bits for writing into an addressed storage location of memory. Error detection and correction encoder circuits are connected to receive the data bits and parity bits and from them generate check code bits which are coded to signal selectively the presence of an uncorrectable error condition in accordance with the parity bits from a given source. During a read cycle of operation, error detection and correction decoder circuits connected to the memory in response to the data and check code bits read out from an addressed location are operative to generate a number of syndrome bits having a predetermined characteristic for indicating the existence of an uncorrectable error condition when the parity bits associated with data signals when written originally into memory if checked would have indicated that the data was in error.

Autocorrelation function factor generating method and circuitry therefor

Abstract: For a delta modulated signal wave comprising a digital carrier wave modulated by an analog wave and represented accordingly as a bivalued digital data bit stream, a correlation function factor is generated by delaying the bit stream in time by an integral multiple of bits and accumulating the successive individual products over a predetermined number of bits of successive individual bits delayed in time and the corresponding currently appearing bits. The circuitry is extremely simple; readily procurable components only are required. A dual input exclusive OR (XOR) gating circuit is connected to the source of delta modulated signal bit stream and to an N-bit digital binary shift register also connected to the source. A stream of successive bivalued products of the current bits and the time delayed bits over a period of N-bits is obtained from the XOR gating circuit and applied to a bidirectional digital counting circuit from which an autocorrelation function factor is delivered.

Digitally sampled high speed analog to digital converter

Abstract: An analog to digital converter includes a first parallel comparator network receiving the analog signal and continuously producing the most significant bits of the digital signal, a subtractor for removing from the analog signal the amplitude portion corresponding to the most significant bits, a second parallel comparator receiving the modified analog signal and continuously producing the least significant bits of the digital signal, and a sampling buffer responsive to a sampling pulse to provide the digital signal only at the occurrence of the sampling pulse.

Modular binary half-adder

Abstract: Half-adder logic modules employing separate summing and carry circuitry are used in the construction of a modular binary half-adder. Carry bits of less significant digits are calculated independent of and prior to the calculation of corresponding sum bits, thus allowing rapid propagation of such carry bits to more significant digits and subsequent parallel summation of the sum bits using the carry bits previously calculated.

Data bit compression system

Abstract: A binary data signal compression system which includes means responsive to a first selected group of bits of the binary data signal, which is less than the total number of bits of the binary data signal, for producing a second selected group of bits which is less than the first selected group of bits but which contains information corresponding thereto. The second selected group of bits and the remaining bits of the binary data signal are hereupon combined to provide the desired compressed binary data signal.

Common control constant shift reframe circuit

Abstract: COMMON CONTROL CONSTANT SHIFT REFRAME CIRCUIT Abstract of the Disclosure The disclosed reframe circuit utilizes common control circuitry to carry out a reframing operation for any, or all, of a plurality of time division multiplexed digital data groups which are out-of-frame. An old data store is used to store a given number (m) of selected data bits, of each digital group, for two frames for framing comparison purposes. A reframe comparator serves to com-pare, for each digital group, the m bit output of the old data store with m data bits that are two frames later in time. A suitability store is used to record, for each group, which of the compared m data bits have had framing pattern violations and which appears as a suitable candi-date for the framing bit. Based on the present set of comparisons and past suitabilities, a shift decoder searches for the framing bit within the current m-bit window until it has either marked all m bits unsuitable or has found the true framing bit within the window. If all m bits are unsuitable, the data bits of an out-of-frame digital group are shifted m bit positions, m new bits are loaded into the old data store, the suitability store is initialized for these new m bits, and the described operation is repeated. When the shift decoder finds a bit that is suitable for a given number of consecutive frames and hence is the true framing bit, the digital group is placed in-frame by shifting the data bits thereof one to m bit positions.