scispace - formally typeset
Search or ask a question

Showing papers on "Effective number of bits published in 1978"


Patent
26 Dec 1978
TL;DR: In this article, an error feedback circuit is employed in a digital filter to significantly lower noise in the output by feeding back the least significant (roundoff) output bits of the quantizer rather than throwing these bits away as is done in the prior art.
Abstract: An error feedback circuit is employed in a digital filter to significantly lower noise in the output by feeding back the least significant (roundoff) output bits of the quantizer rather than throwing these bits away as is done in the prior art. The feedback circuit for accomplishing this end result includes a digital delay circuit which receives the roundoff bits and delays these bits for a sampling sequence (Z -1 ) (as is also done for the rounded bits), a multiplier which multiplies the output of the delay circuit by a predetermined integer and an adder which subtracts the output of the multiplier from the delayed filtered digital output signal which has been multiplied by a predetermined constant.

18 citations


Patent
19 Sep 1978
TL;DR: In this article, an overflow detect and correct recursive digital filter for dealing with data words given by two's complement representation in a common word format comprising a sign bit, an integer bit, and a predetermined number of fractional bits is presented.
Abstract: In a recursive digital filter for dealing with data words given by two's complement representation in a common word format comprising a sign bit, an integer bit, and a predetermined number of fractional bits, an overflow detect and correct circuit is supplied with simultaneously produced sign bits of bit-serial first sum, feedback, and second sum data words and with the integer bit of the second sum data word and detects overflow in the second sum data word to produce, for use in the circuit, an overflow detect pulse indicative of presence or absence of overflow. In either event, the circuit produces an overflow-free data word for use in the filter. When overflow is detected, the circuit produces a polarity decision pulse that decides polarities of the overflow-free bits. Otherwise, the circuit determines the overflow-free bits directly by the corresponding bits of the second sum data word. Use is preferred of a first and a second timing signal which specify time slots for the sign bit and a prescribed bit, respectively, of each serial data words and which are for directly deciding the overflow-free fractional bits by the polarity decision pulse and for producing a second polarity decision pulse for direct decision of polarities of the overflow-free sign and integer bits. A memory having a plurality of memory areas is preferred for production of the overflow detect and the polarity decision pulses and of the overflow-free bits.

17 citations


Patent
25 Sep 1978
TL;DR: In this paper, a pseudo-random bit generator is proposed to produce a noise signal as a function of the number of parallel bits generated at each clock pulse, which are successive bits of a pseudo random sequence.
Abstract: The disclosure is directed to an apparatus and method for generating noise having characteristics of repeatability and reproducibility. A pseudo-random bit generator is responsive to clock pulses for simultaneously generating, at each clock pulse, a plurality of parallel pseudo-random digital bits which are successive bits of a pseudo-random sequence. In particular each new plurality of parallel bits is a successive group from the same pseudo-random sequence, thereby insuring a maximum number of totally uncorrelated groups. The bits generated at each clock pulse are operated on to produce an output noise signal as a function of the plurality of pseudo-random parallel bits generated at that clock pulse. In an embodiment of the invention, the operation on the plurality of bits comprises summing the value of the bits to produce a noise signal, the noise signal exhibiting a substantially Gaussian distribution with time. In another embodiment of the invention, the operation on the plurality of bits comprises comparing a first group of the plurality of bits to a second group of the plurality of bits and generating an output signal, at each clock pulse, as a function of the comparison. The output signal thereby occurs at substantially random intervals and constitutes a substantially random distributed noise signal.

16 citations


Patent
30 May 1978
TL;DR: In this paper, an analog-to-analog converter is coupled to a successive approximation register for providing an indication of whether the value of the most significant bits is other than zero.
Abstract: An expanded analog-to-digital converter includes a first digital-to-analog converter for converting the most significant bits of digital output signal having a given number of bits to a first analog reference signal having a value that is proportional to the value of the most significant bits minus one-half the least significant bit of the digital output signal whenever the value of the most significant bits is other than zero; and a second digital-to-analog converter for converting the least significant bits of the digital output signal to a second analog reference signal. A successive approximation register successively provides the bits of a digital output signal in accordance with a comparison of an analog input signal with the sum of the analog reference signals. A logic circuit coupled to the successive approximation register for providing an indication of whether the value of the most significant bits is other than zero, causes the second analog reference signal to have a value that is proportional to the value of the least significant bits whenever the value of the most significant bits is other than zero, and a value that is proportional to the value of the least significant bits minus one-half the least significant bit of the digital output signal whenever the value of the most significant bits is zero.

14 citations


Patent
14 Apr 1978
TL;DR: In this article, a method for reducing the probability of the loss of a character in a digital transmission employing biphase coding is proposed, which comprises the steps of identifying the bits out-of-code, that is the bits which don't correspond to the two Biphase code configurations; complementing the logic value said bits are given by the demodulator, if there is parity error; inhibiting a character not comprising outofcode bits, but in which parity error occurs or if two or more outof code bits are present in the character.
Abstract: A method for reducing the probability of the loss of a character in a digital transmission employing biphase coding which comprises the steps of identifying the bits out-of-code, that is the bits which don't correspond to the two biphase code configurations; complementing the logic value said bits are given by the demodulator, if there is parity error; inhibiting a character not comprising out-of-code bits, but in which parity error occurs or if two or more out-of-code bits are present in the character. The circuit implementing the method comprises shift register means for storing the information bits and control signals identifying the out-of-code bits; parity check means; complementing means for complementing the logic state which are given by the demodulator to the out-of-code bits, said complementing means being conditioned by the simultaneous occurrence of the out-of-code bit and the parity error in a character; logic means for inhibiting the character in presence of parity error alone or of two or more out-of-code bits.

7 citations


Patent
15 Dec 1978
TL;DR: In this article, an interpolative PCM decoder was proposed to convert PCM signals having polarity bits, segment selection bits and uniform quantization bits into an analog signal.
Abstract: An interpolative PCM decoder converts PCM signals having polarity bits, segment selection bits and uniform quantization bits into an analog signal. The PCM decoder may be used both for μ-law and A-law conversion by use of simple circuits and includes an AND gate circuit which produces a logical product between a selection signal for selecting a minimum unit of an analog value of a lower end of a segment and a control signal for change-over between the μ-law and the A-law, and a circuit generating the same analog values as the minimum unit of the analog value in accordance with an output of the AND gate circuit.

7 citations


Patent
18 Dec 1978
TL;DR: In this paper, a digital drive current for application to a variable-speed electric motor is generated from a binary signal including N high-order bits and n low-order bit, and a pulse waveform of fixed frequency higher than the frequency to which the motor can respond is generated to have a pulse width duty cycle in accordance with the value of the high order bits.
Abstract: A digital drive current for application to a variable-speed electric motor is generated from a binary signal including N high-order bits and n low-order bits. A pulse waveform of fixed frequency higher than the frequency to which the motor can respond is generated to have a pulse width duty cycle in accordance with the value of the high-order bits. The low-order bits are used to make a one-step increase in the width of a proportion, determined by the value of the low-order bits, of the pulses of the pulse waveform, so that the average pulse width is increased a desired fraction of one step.

5 citations


Journal ArticleDOI
TL;DR: In this article, a precision analog-to-pulsewidth converter has been achieved with pulsewidth modulation technique and new circuit designs applied to a standard bipolar monolithic IC process, where the magnitude and polarity of the input Information are determined by the pulsewidth modulated output signal within 0.002-percent linearity error and \pm 10 PPM/°C full-scale and zero-scale drift at low conversion rate.
Abstract: A precision analog-to-pulsewidth converter has been achieved with pulsewidth modulation technique and new circuit designs applied to a standard bipolar monolithic IC process. The magnitude and polarity of the input Information are determined by the pulsewidth modulated output signal within 0.002-percent linearity error and \pm 10 PPM/°C full-scale and zero-scale drift at low conversion rate. Although the low-frequency noise in EC buffer limits the actual resolution of the converter to 13 bits, the externally connected Zener diode in EC output reduces the EC noise, and the resolution increases to 15 bits which is consistent with the linearity of the converter.