Showing papers on "Effective number of bits published in 1979"

Compression of the ECG by Prediction or Interpolation and Entropy Encoding

Abstract: Compression of digital electrocardiogram (ECG) signals is desirable for two reasons: economic use of storage space for data bases and reduction of the data transmission rate for compatibility with telephone lines. In a sample of 220 Frank4ead ECG's the removal of signal redundancy by second-order prediction or interpolation with subsequent entropy encoding of the respective residual errors was investigated. At the sampling rate of 200 Hz, interpolation provided a 6 dB smaller residual error variance than prediction. A near-optimal value for the interpolation coefficients is 0.5, permitting simple implementation of the algorithm and requiring a word length for arithmetic processing of only 2 bits in extent of the signal precision. For linear prediction, the effects of occasional transmission errors decay exponentially, whereas for interpolation they do not, necessitating error control in certain applications. Encoding of the interpolation errors by a Huffman code truncated to ±5 quantization levels of 30 ?V, required an average word length of 2.21 bits/sample (upper 96 percentile 3 bits/sample), resulting in data transmission rates of 1327 bits/s (1800 bits/s) for three simultaneous leads sampled at the rate of 200 Hz. Thus, compared with the original signal of 8 bit samples at 500 Hz, the average compression is 9:1. Encoding of the prediction errors required an average wordlength of 2.67 bits/sample with a 96 percentile of 5.5 bits/sample, making this method less suitable for synchronous transmission.

Error correction and detection systems

Abstract: In a system which employs SEC-DED codes constituted by data bits added to redundant bits and is capable of detecting and correcting a single bit error while detecting a double or more bit error, detection is made on miscorrection ascribable to a triple bit error. When a single bit error is detected by an error detecting and correcting circuit in the SEC-DED code read out from a memory, all the corrected data bits are inverted in state and rewritten in the memory after having been added to new redundant bits. Subsequently, the data bits together with the redundant bits are read out from the memory and supplied to the error detecting and correcting circuit. The data bits obtained from the error detecting and correcting circuit are compared with the corrected and inverted data bits available before being written in the memory, to thereby determine the presence of an error encompassing more than (m+1) bits on the basis of the result of comparison.

Digitally adjustable phase shifting circuit

Abstract: A counter produces, as a function of time, an M bit count of cycles of a periodic signal. A storage device stores a changeable value represented by N bits comprising M higher order bits and N-M lower order bits. An adder produces M bits corresponding to the sum of M counter bits and M higher order bits. A digital-to-analog converter produces an alternating signal corresponding to the value of the M summed bits and N-M lower order bits where the phase of the alternating signal relative to an arbitrary reference signal corresponds to the value stored in the storage device.

Analog-to-digital converter: a new type using an electrooptic light modulator

Abstract: A new type of analog-to-digital converter (ADC), which consists of an electrooptic light modulator and electronic diode circuits, is proposed. This device allows direct translation of an analog signal into a Gray code with high speed and high resolution. It is demonstrated that an analog signal with a 60-V P–P voltage and a frequency of 11 MHz can be translated into 3 bits in a Gray code by this ADC.

Gain control apparatus for digital telephone line circuits

Abstract: There is disclosed a digital gain control particularly adapted for use with digital signals propagating in a telephone line circuit. The gain control is positioned in the circuit to respond to a digital signal manifesting a plurality of words, each having a given number of bits N and indicative of a weighted value of an analog signal. The digital signal is multiplied by a word coefficient having a number of bits M indicative of a gain factor to be imparted to the digital signal. A product signal is provided containing M+N bits. The least significant bits are removed to provide an output signal of N bits possessing the desired gain. The discarded bits are employed via a feedback loop and are added to the next word product, which is then used to provide a next output signal. The feedback loop assures that each output signal is a close approximation to the input signal as gain controlled by the desired gain factor.

Digital signal transmitting method

Abstract: PURPOSE: To make it possible to transmit data and a word sink (WSD) signal via one transmission line by using the word sink (WSD) signal in different format from the data in a digital signal series transmitting method. CONSTITUTION: Period Tws of WSD signal A is equally divided by thirty two to obtain a digital signal of 32 bits for one word and the unit time of one bit is denoted as T. Then, 20 bits from the 1st bit MSB to 20th bit are used for sampling data, and 12 bits from the 21st bit to the 32nd bit are used as control bits and user's bits. Three bits, the 30th, 31st and 32nd bits, are used for a WSD signal and bits from MSB to the 29th bit are used for an NRZ signal of T in unit time; and the WSD signal is made into the unit time 1.5T NRZ signal to change both the signals in format and while the signal for 32 bits is transmitted in series via one transmission line to a receiver, a word sink extracting circuit in the receiver extracts the WSD signal, so that data bits in one word will be read on the basis of this WSD signal. COPYRIGHT: (C)1981,JPO&Japio

Frame structure for third order digital TDM system - has every 512 signal bits preceded by 25 additional bits for synchronisation, timing and alarm signals

Abstract: The frame is suitable for transmission and switching, with information for synchronisation and signalling timing deviations, containing two timing adjustment commands, alternating in case of synchronism. In order to combine 16 wideband channels or PCM-30- basic systems, each with 2.048 Mbit/s into a signal flow of 34.368 Mbit/s, each 512 information bits are preceded by 25 additional bits. The first 12 bits serve for synchronisation, 13th to 16th bits allocate timing deviation signals to a subsystem, 17th bit signals positive timing deviation, 18th bit a not urgent alarm, 19th bit an urgent alarm, and remaining bits are reserved for international problems.

Data transmission system as well as method and circuit arrangement for running such a data transmission system

Abstract: 1. Data transmission system comprising data-emitting and data-receiving data channels, wherein the data bits together with control bits are synchronously transmitted in envelopes, characterized in that each envelope posseses data bits of at least two data-emitting data channels, and that the control bits are utilized as sole synchronizing information for a bit synchronization and bit group synchronization.

Floating point processor architecture which performs subtraction with reduced number of guard bits

Abstract: There is provided a circuit and method for subtracting floating point numbers which are represented by binary bits. In this circuit, the smaller number (minuend) in one register is arranged so that the complement thereof is denormalized and added to the subtrahend (i.e. larger number) and the result of the addition is returned to the original register. At that time, the signal stored in the register is renormalized. In this circuit, the number of guard bits required to guarantee round off accuracy is only two.