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Showing papers on "Effective number of bits published in 1980"


Patent
Baard H. Thue1
28 Apr 1980
TL;DR: In this article, a digital pulse compression radar system with interrupted, phase coded, high duty ratio transmissions which allow contiguous range resolution cells to be established in coverage space and provide adequate airframe impulse excitation recovery time is presented.
Abstract: A digital pulse compression radar system with interrupted, phase coded, high duty ratio transmissions which allow contiguous range resolution cells to be established in coverage space and provide adequate airframe impulse excitation recovery time to render high duty ratio, phase coded, radar feasible for airborne applications. Each pulse is subdivided into a predetermined number of subpulses or bits, which are phase coded with (in-phase or out-of-phase) reference to a master oscillator. In the preferred embodiment, the code is built up from a PRN code staggered over 2 n-1 pulses, each containing m resolution elements, where n is an arbitrary number designating the degree of the code and where m is an arbitrary number or is equal to the number of bits per pulse. The correlation properties of the code are such that when all bits of the returned pulses representing a word align with the delayed transmitted word, all bits add. When the bits do not align precisely, the bits generally cancel each other. Because of this, partial pulse overlaps do not produce a noticeable effect and ambiguity of the range is no longer limited by the time separation of adjacent pulses.

43 citations


Patent
30 Jun 1980
TL;DR: In this paper, a coding scheme is implemented which uses through checking parity bits appended to each byte as check bits, and the remaining check bits are generated such that the combination of through-checking parity bits and remaining check bit together provide single bit error correction and double bit error detection.
Abstract: Apparatus for and method of providing single bit error correction and double bit error detection using through checking parity bits. A coding scheme is implemented which uses through checking parity bits appended to each byte as check bits. The remaining check bits are generated such that the combination of through checking parity bits and remaining check bits together provide single bit error correction and double bit error detection.

42 citations


Journal ArticleDOI
TL;DR: An A/D converter circuit system with a very high bit-rate has been developed, and the input of the last A/ D stage is equivalently ac-coupled, which can be allowed by the statistical charactertstics of input signals.
Abstract: An A/D converter circuit system with a very high bit-rate has been developed. It is a series-parallel type, and the input of the last A/D stage is equivalently ac-coupled. This can be allowed by the statistical charactertstics of input signals. A prototype of this A/D converter has the following characteristics: 1) dc coupled analog input-able to accept almost all analog signals as well as television signals; 2) sampling frequency up to 20 MHz; 3) linear coding scheme with 10 bits per sample; 4) linearity error of less than one third of quantizing level; 5) differential gain and differential phase of 0.4% and 0.25°, respectively; and 6) operating temperature range of from 0° to 50°C.

4 citations