Showing papers on "Effective number of bits published in 1983"

Synchronization of real-time clocks in a packet switching system.

Abstract: A packet switching system in which a remote real-time clock is accurately synchronized to a standard real-time clock via X.25 (CCITT) controlled high-speed transmission links. Synchronization is achieved by the transmission of an interrupt packet and a data packet between a remote processor controlling the remote real-time clock and an administrative processor controlling the standard real-time clock. Synchronization involves the following steps: (1) assembling an interrupt packet comprising the least significant bits of the remote real-time clock for transmission to the administrative processor by the remote processor, (2) calculating bits representing the difference between the transmitted least significant bits of the remote real-time clock and the least significant bits of the standard real-time clock by the administrative processor, (3) assembling a data packet comprising bits representing the state of the standard real-time clock and the difference bits for transmission to the remote processor by the administrative processor, (4) adding the difference bits to the bits representing the state of the remote real-time clock by the remote processor, and (5) adding a predefined value to the most significant bits of the remote real-time clock by the remote processor if the transmitted least significant bits of the standard real-time clock are numerically greater than the least significant bits of the remote real-time clock.

Radian reduction for trigonometric functions

Abstract: An accurate reduction poses little difficulty for arguments of a few radians. However for, say, a CRAY1, H format on the VAX, or double extended in the proposed IEEE standard, the maximum argument which might be presented for reduction is of the order of 2^16000 radians. Accurate reduction of such an argument would require storage of π (or its reciprocal) to over 16,000 bits. Direct reduction by division (or multiplication) then requires generation of a somewhat larger number of bits in the result in order to guarantee the accuracy of the reduction. Of these bits only the low few bits of the integer part of the quotient (product) and enough bits to correctly round the remainder are relevant; the rest will be discarded.

Pseudo-random convolutional interleaving

Abstract: A method and apparatus for interleaving and deinterleaving psuedo-randomly a digital signal which is transmitted over a transmission channel is disclosed. A received bit stream is interleaved such that the order of the bits is varied in a non-random manner. The order of the interleaved bits is permutated in a pseudo-random manner and the bits are then transmitted over a transmission channel. The received bits are inverse permuted so as to return the order of the received bits to the order of the bits after the non-random interleaving step. The inverse permuted bits are then deinterleaved in the reverse order in which they were interleaved so as to reconstitute the original bit stream.

Read error occurrence detector for error checking and correcting system

Abstract: An improved error indicating system utilizing adder circuits for use with an error correction code system capable of detecting and indicating multiple bit errors and detecting and correcting single bit errors is described. The system utilizes an encoding system for generating a plurality of check bits, each check bit associated with a predetermined bit grouping of data bits within a data word. When a data word is accessed, read check bits are reconstituted from the read data and are compared to the check bits originally encoded. Syndrome bits are generated from the originally encoded check bits and the reconstituted read check bits, the syndrome bits thus generated, serving to identify whether the data word accessed contains no errors, a single bit error, or a multiple bit error. Decoder circuitry for decoding the syndrome bits and effecting the control signals for controlling the correction of single bit errors is described. The syndrome bits are applied to the adder circuits in predetermined groupings, and the carry signals from each of the adder circuits are applied to circuitry for detecting the occurrence of multiple bit errors. Selected ones of the decoded syndrome bits are utilized to determine the occurrence of single bit errors.

Digital to analog converter utilizing pulse width modulation

Abstract: A pulse width digital to analog converter is constructed which provides an output clock rate that is a multiple of the input sampling rate. In one embodiment a latch is used to store N-bit digital word representing the analog signal value to be generated. (N-K) of the most significant bits are stored in a counter which decrements its count in response to a clock signal. A plurality of least significant bits of said digital word stored in said latch are applied to a logic circuit. A ring counter is utilized to indicate which section of the output signal is currently being generated. The plurality of the least significant bits of the digital word stored in the latch, together with the output signals from the ring counter, are applied to said logic circuit, and the transition of the output signal of the digital to analog converter from a logical one to a logical zero is delayed, when required, to provide a slightly increased output pulse width in response to said plurality of least significant bits of said digital word, thereby maintaining or even increasing the resolution of the system.

Device for enciphering digital signals comprising one or more DES circuits

Abstract: Circuit provided with a number of data encryption standard circuits (DES). In order to obtain a greater interaction between the key bits and the data bits, at least two DES are connected in series, and a number of bits of the output of a first DES is directly supplied to the input of a second DES, which number of bits is at the same time added modulo 2, modulo 4 to the bits of an equal number of other outputs of the first DES. Even if the same key should be supplied to both DES and if, due to an operating error, the first DES should have been set to encipher and the second DES should have been set to decipher, the clear text will be prevented from appearing at the output. At the same time a good protection against so-called weak keys is obtained.

Medium speed multiples data

Abstract: Synchronization can be acquired between a transmitting node and a receiving node on a time division multiple access communication link without the necessity for additional data bits in the data stream, by correlating the number of errors detected in any interval as revealed by the forward error correction field. Both synchronization bits and stuffing bits can be located without using any external frame timing information. Substantial bandwidth savings is achieved by the technique, which can be applied for arbitrary combinations of the number of input ports, the number of data bits per group, and the number of parity bits generated per group.

Expansion circuit for digital signals

Abstract: A PCM signal processor which converts an analog signal into a digital signal to transmit or record the digital signal. When the PCM signal processor receives a PCM signal whose data has been compressed in such a manner that one or more lower bits are cut off from a plurality of bits for forming the PCM signal and indicating the signal level of the analog signal, in accordance with the signal level of the analog signal, one or more bits corresponding to the number of bits having been cut off are added in the processor to the compressed PCM signal at the position following the least significant bit of the compressed PCM signal (9). Correction data indicating about one half the largest one of numerical values that can be expressed by the added bit or bits, is given to the added bit or bits (30, 31; 26).

PROM trimmed digital-to-analog converter

Abstract: A digital-to-analog converter apparatus (DAC) includes internal PROM-controlled compensating converter means for precisely compensating values of lesser significant bits in accordance with scale factors which depend upon the binary input values of more significant bits and which are independent of compensation of the analog output signal value corresponding to the more significant bits. The converter apparatus employs programmable read-only memory (PROM) for decoding input digital values into digital compensation values which control internal digital-to-analog converter apparatus. An analog signal out of an internal compensating digital-to-analog converter apparatus is coupled to a summing junction and an analog scaling reference. The output of the summing junction generates a compensated analog scaling value signal which is fed to a reference terminal of a digital-to-analog converter apparatus which generates the analog signal representing the lesser significant bits.

Address signal generating circuit for a memory circuit

Abstract: An address signal generating circuit for a memory circuit comprises a first latch driver for producing a signal corresponding to upper m bits of a 2m-bit address signal which is to be generated, where m is an integer, a second latch driver for producing a signal corresponding to lower m bits of the 2m-bit address signal, a circuit for dividing a 2m-bit signal which has a predetermined value into upper m bits and lower m bits and for alternately producing signals corresponding to the upper and lower m bits, a first adder for adding the value of n bits in the signal which has the predetermined value and the value of upper n bits in an output signal of the first or second latch driver and for producing an n-bit signal, where n is an integer less than m, a second adder for adding the value of m-n bits in the signal which has the predetermined value and lower m-n bits of the output signal of the first or second latch driver and for producing an (m-n)-bit signal, an adding circuit for supplying a carry signal of the first or second adder to the second or the first adder so as to add the carry signal with another input signal of the second or the first adder, and a driver control circuit for controlling the first and second latch drivers to alternately and time-divisionally produce upper m bits of the 2m-bit address signal and lower m bits of the 2m-bit address signal by alternately latching an m-bit output signal of the first and second adders in the first and second latch drivers.

Code modulating system

Abstract: PURPOSE:To attain transmission of high rate to a transmission system having a band limit and decreased low-frequency spectrum by converting data of 8 bits into a code word 10 bits, applying NRZI modulation thereto and transmitting the result to make the bit synchronism at the reproducing side easy. CONSTITUTION:Input data of 8 bits is converted into a parallel signal at a shift register 1 and inputted to an ROM 2 storing the conversion rule of 8 bits into 10 bits, and a block signal of 10 bits thus obtained is converted into a serial signal at a shift register 3, modulated at an NRZI modulator 4 and transmitted to a transmission line. On the other hand, data from the transmission line is demodulated into an NRZ signal at an NRZ demodulator 5, demodulated into an NRZ signal, converted into a parallel signal of 10 bits at a shift register 6, inputted to an ROM7 storing the inverse conversion rule of 10 bits into 8 bits, the data of 8 bits thus obtained is converted into a serial signal at a shift register 8 and transmitted to a data processing system.

Integrated weighted current digital to analog converter

Abstract: A weighted current digital to analog converter (DAC) translates digital bits to corresponding analog signals by a suitably operated transfer circuit of (1) multiple parallel current sources for more significant bits and (2) binary weighted current sources for lesser significant bits. The number of resistors and the ratio of adjacent resistors is reduced in the transfer circuit relative to a ladder type DAC. Power saving and linearity are improved by the reduced number and ratio of adjacent resistors. The transfer circuit facilitates fabrication of the DAC in a semiconductor. Temperature stability is improved by proper location of the current sources in the semiconductor.

Digital to analog converter having integrated digital and analog circuitry

Abstract: A D/A converter for converting a digital signal having a number of bits to an analog signal. The converter is fabricated in an integrated circuit digital array including a register for storing the particular number of bits, a buffer circuit for receiving those bits from the register, and an analog current switching network. The analog current switching network includes a number of current switching circuits, each of which provides the proper current output in response to the delivery of an associated bit from the buffer circuit. Each current switching circuit includes an emitter coupled switch circuit having two pluralities of parallel connected transistor cells with the bases of one of the plurality of transistor cells connected with the buffer circuit and the bases of the other of the plurality of transistor cells connected with the current switching circuit. The current switching circuit includes a first transistor cell with its emitter connected to the base of the other of the plurality of transistor cells in the emitter coupled switch circuit. A voltage summing network responsive to the current output from the analog current switching network provides voltages representative of the bit presented by the associated buffer circuit.

Deflection system in an electron beam exposure device

Abstract: in a D/A converter in a deflection system of an electron beam exposure device, the most significant bits (m bits) of input digital data consisting of n bits are input into a decoder circuit, and 2 m D/A converters which correspond to the m bits are provided. The data consisting of the least significant bits (n-m bits) is input into the 2 m D/A converters via 2 m gates, respectively. The decoder circuit is constructed so as to control the 2 m gates so that when the content of the data of the m bits is S, the first to S-th data of the 2 m D/A converters is all rendered to be "1", the data of the (S+1)-th D/A converter remains the same as the data of the n-m bits, and the data of the (S+2)-th and subsequent D/A converters is all rendered to be "0", the sum of the outputs of the 2 m D/A converters being applied to a coil which deflects the electron beam.

Method for operational monitoring of digital transmission paths

Abstract: A method for operational monitoring of digital optical waveguide transmission paths is indicated in which the bits are combined to form data words and transmitted along with check bits which are added to the data words in each case in the same position. Check bits are generated at the receiving end in the same way as at the transmitting end and are compared with the check bits extracted from the data stream. The evaluation, at the receiving end, of the check bits which are independent of the actual information allows the bit error rate to be determined.