Showing papers on "Effective number of bits published in 1985"

Method and apparatus for improving the accuracy and resolution of an analog-to-digital converter (ADC)

Abstract: A system for increasing the accuracy and resolution of an ADC comprising a digital filter connected to the output of the ADC, a system clock for providing a digital filter clock signal, a low/pass filter/amplifier for generating a large-scale, rapidly varying dither signal fdrom the digital filter clock signal, and a summing circuit for adding the dither signal to a test signal connected to the input of the ADC.

Method and device for correcting errors in memories

Abstract: The bit configurations are arranged in M-bit code words, each word comprising a number D of data bits and an even number N of error correcting bits. The data bits are partitioned into N fields with an error correcting bit associated with each field to indicate the parity of the associated field. The assignment of data bits to the N fields in such that, when the N fields are used to generate an N-bit error syndrome, this syndrome will contain an odd number n1 of bits at a first value if there is a single bit in error, where N-n1=n2 is also odd, and an even number of bits different from N to indicate a two-bit error. The number of bits of the first value are then used to determine whether the codeword is in its true or inverted form.

Method of correcting errors of digital signals in the recording and reproduction of digital signals

Abstract: Parity bits (check bits) having a relatively high redundancy are added to upper significant bits of a digital signal, and parity bits having a relatively low redundancy, are added to the lower significant bits of the digital signal. The signal and the parity bits are recorded on a recording medium. The position of an error in a data block group of the lower bits reproduced from the recording medium is estimated as existing in a block in which the error is detected by the check of the data block group of the upper bits, and in the blocks preceding and subsequent to the former. This error correction method is most suitable for a recording and reproduction system of digital video signals.

Error monitor circuit

Abstract: A multi-value signal monitor circuit in a data transmitting and receiving system which transmits data after conversion into a multi-value signal and obtains the original data through analog-to-digital conversion of the received multi-value signal. The data is converted more accurately than the number of bits of data transmitted, during the analog-to-digital conversion on the receiving side. The position of the received signal relative to the quantization level is determined by utilizing the extra bits. When the extra bits indicate the multi-value signal is outside the specified range of the quantization level a pseudo error is detected. The pseudo errors are counted to produce a pseudo error rate which is used as an error rate for transmission path switching purposes.

System for transmitting words that are protected by a combination of a block code and a convolution code, transmitter device for use in such system and receiver for use in such system

Abstract: A system is described for transmitting data words composed of more significant bits and less significant bits. The less significant bits of a data word are, by means of matrix multiplication, encoded into a first redundant proto-code word. The more significant bits of a data word are by means of matrix multiplication, and different delays over respective numbers of recurrence times of the arrival of the data words encoded in a set of further redundant proto-code words. A code word is formed by means of modulo-2-addition of code words, so that for the less significant data bits a block code is realized, while for the more significant data bits a convolutional encoding is realized. In the decoding, the more significant bits are decoded by means of Viterbi decoding, while the Viterbi metric is determined from the deviation between the reconstructed contribution from the lower significant bits and the actually received contribution therefrom.

Frame alignment loss and recovery device for a digital signal

Abstract: A frame alignment loss and recovery device for a digital signal carrying a frame alignment N-bit word comprises an (N+2)-stage shift register receiving the digital signal at a timing frequency H, a buffer register for extracting (N+2)-bit words from the shift register at a frequency H/3, a logic circuit for comparing each extracted word with three predetermined (N+2)-bit words respectively including N last bits, N central bits and N first bits identical to the alignment word bits in the signal, and a circuit for deriving a frame synchronization pulse in phase with the start of an alignment word contained in an extracted word having bits respectively identical to like-ranked bits in one of the three predetermined words. Because searching for the alignment word is at a frequency H/3, the logic circuit can include conventional PROM memories and alignment word errors can be tolerated despite a digital signal of high rate, for example, 34 Mbit/s.

Method and apparatus for quasi-analog reconstructions of amplitude and frequency varying analog input signals

Abstract: A high level, staircase type of quasi-analog reconstruction of an analog input signal, such as an audio signal, initially involves a conventional derivation of a PCM signal from the analog input signal. The binary bits of each PCM codeword are considered as being C in number, of which an A number are major bits and a B number are minor bits. The A number of bits are converted to (2 A -1) discrete decimal data bits, each of which controls the switching to and from a series voltage summation line of a discrete voltage V c , where ##EQU1## and V max is substantially the peak kilovolt amplitude to be provided in the reconstructed signal. Individual ones of the B bits directly control the individual switching to and from the summation line of discrete voltages of unequal magnitudes declining in one-half voltage increments from Vc/2 to Vc/2 B . Alternatively, individual bits of N more significant bits of the B bits directly control the individual switching to and from the summation line of discrete voltages of unequal magnitudes declining in one-half voltage increments from Vc/2 to Vc/2 N , while the remaining (B-N) bits are converted, in combination, to an analog control voltage which drives a step voltage follower whose output is permanently connected in series with the summation line to add thereto a step voltage in the range of from Vc/2 N+1 to Vc/2 B where the step voltages decline in one-half voltage increments.

IC chip error detecting and correcting apparatus

Abstract: Error detecting and correcting operations for a plurality of input bits comprised of input data bits and associated check bits are implemented using two IC chips in order to overcome chip output limitations. The use of two identical IC chips for this purpose is made possible by employing a specially chosen inversely symmetrical Hamming code and by wiring the input data bits and the input check bits in an inverse manner with respect to the input terminals of the two IC chips. As a result, even though each IC chip performs the same error detecting and correcting operations, it does so inversely with respect to the input data bits and the input check bits so that each IC chip is able to provide one-half of the required output bits.

IC chip error detecting and correcting method

Abstract: A method employing two identical IC chips for providing error detecting and correcting operations on a plurality of input bits comprised of input data bits and input check bits, wherein a single one of the IC chips has an insufficient number of available outputs to provide all of the required outputs. The method includes applying the input data bits and the input check bits to the input terminals of each IC chip in an inverse manner relative to one another, and then performing the error detecting and correcting operations on each chip in accordance with an inversely symmetrical Hamming code. As a result, even though the same detecting and correcting operations are performed on each IC chip, they are performed in an inverse manner with respect to the input data and input check bits so that each IC chip is able to provide one-half of the required output bits.

Multi-state signal monitor circuit

Abstract: A multi-state signal monitor circuit for a data transmission system which transmits a plurality of bits of data after conversion into a multi-state signal and obtains original data of plural bits through analog-to-digital conversion of the received multi-state signal. Data is discriminated more precisely than the number of bits of data of a plurality of bits on the occasion of analog-to-digital conversion in the receiving side (10B) and the focusing degree of the received signal to the quantization level is detected by utilizing said extra bits. Thereby the error rate is monitored quickly and accurately with simplified circuits. The monitor circuit comprises an A-D converter (120) and a pseudo error rate measuring circuit (122).

Two stage decoder circuit using threshold logic to decode high-order bits and diode-matrix logic to decode low-order bits

Abstract: A two-stage decoder circuit includes a first-stage decoder circuit, for decoding upper bits of an input signal, and a second-stage decoder circuit, which is activated by receiving a selected output signal of the first-stage decoder circuit and which decodes lower bits of the input signal. The first-stage decoder circuit is formed by a threshold-operation type logic circuit which carries out selection or non-selection by comparing the input signal with a predetermined threshold level, and the second-stage decoder circuit is formed by a diode-matrix circuit.