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Showing papers on "Effective number of bits published in 1987"


Patent
27 Jul 1987
TL;DR: In this article, a 1/2 rate convolutional encoder was used to encode the data and a supplementary coding system was used for converting the encoded data to a nominal 3/4 rate.
Abstract: The system first incorporates an encoder which utilizes a 1/2 rate convolutional encoder to encode the data and a supplementary coding system for converting the 1/2 rate coded data to a nominal 3/4 rate. Thereafter, in order that the encoded data fits within the fixed frame length which has been adopted as a standard for the present TDMA transmission system, a portion of the excess data in each frame of encoded data put out by the encoder must be deleted or punched out. These bits are spaced throughout the frame to minimize the effect of the punchout routine. On the decoding side of the system, bits must be reinserted in the same place where they were deleted in the encoder. Because these bits were removed at the encoder, the decoder cannot possibly know what they were. It is not important to know what they were, but rather when in the received bit stream they would have occurred. In these places, place holding bits that are marked as such are inserted. This function is achieved by arbitrarily inserting either 1's or 0's in the bit stream, and providing an accompanying bit stream which incorporates flag bits for marking the existence of these place holding bits. Later processing in the decoder then simply treats these bits as place holders. That is, they do not add information that can help correct errors, nor do they cause errors.

46 citations


Patent
24 Feb 1987
TL;DR: In this paper, an error-correcting memory system includes a storage module which receives an address during a read cycle and reads data bits and check bits at the address, and it further includes a low DC power logic circuit which corrects errors in the data bits by decoding multiple minterms from the check bits.
Abstract: An error-correcting memory system includes a storage module which receives an address during a read cycle and which reads data bits and check bits at the address, and it further includes a low DC power logic circuit which corrects errors in the data bits by decoding multiple minterms from the check bits; wherein the logic circuit is comprised of: a plurality of logic gates, one for generating each of the minterms by passing a constant power dissipating current to selectively decode the check bits; a control circuit for generating a control signal that is in one state during only a small fraction of the read cycle and is otherwise in an opposite state; and an enabling circuit, coupled between the control circuit and the logic gates, for enabling their selective decoding by permitting the constant current to flow through the gates only while the control signal is in its one state.

35 citations


Patent
28 Dec 1987
TL;DR: In this paper, error detection and correction logic is interposed between a 16-bit CPU and a data storage unit with a 32-bit word size and single bit error correction and double bit error detection (ECC) code bits.
Abstract: Error detection and correction logic is interposed between a 16-bit CPU and a data storage unit with a 32-bit word size and single bit error correction and double bit error detection (ECC) code bits. During each CPU Read cycle, a full word and its ECC bits are read from storage; and a selected 16 data bits are transferred to the CPU directly if they are error free or are corrected by the ECC logic and then transferred if they have only one bit with an error. During each CPU Write cycle, a selected full word and its ECC bits are read from storage; 16 data bits of the word are replaced by 16 data bits from the CPU; ECC bits are calculated for the modified word; and the modified word and its ECC bits are entered into the storage unit so long as no error exists in the remaining 16 bits of the data word which were not replaced/modified. This type of operation is often referred to as a Read-Modify-Write (RMW) cycle. During this RMW operation, the ECC logic detects and corrects a single bit error (if one exists) concurrent with modification of the word and calculation of new ECC bits. The corrected word is then modified by the data bits from the CPU, new ECC bits are calculated and the latter modified word and ECC bits are entered into the storage unit rather than the former word which contained a single bit error. If no error exists, a short RMW cycle is used; if a single bit error exists a longer RMW cycle is used.

25 citations


Patent
Hideaki Morimoto1
30 Mar 1987
TL;DR: In this paper, an error-correcting encoder and decoder are synchronized with framing bits to minimize the effect of a timing disruption which occurs briefly if the transmit DPU of a faulty regular channel is switched to the error correcting encoder of a standby channel.
Abstract: A digital radio transmission system comprises a transmit digital processing unit that compresses the time scale of a prescribed number of consecutive data bits for leaving a time interval between adjacent time-compressed data bits, generates an additional bit and inserts it into a portion of the time interval immediately following the time-compressed data bits to form composite bits. An error correcting encoder performs computations on the composite bits according to an encoding theorem and inserts an error correcting code into the remainder of the time interval, forming a block code. An error correcting decoder performs computations on the block code according to a decoding theorem for correcting error in the composite bits. A receive digital processing unit separates the additional bit and the time-compressed data bits of the error-corrected composite bits and expands the time scale of the separated time-compressed data bits. To ensure fast channel switching the error correcting decoder is synchronized with framing bits to minimize the effect of a timing disruption which occurs briefly if the transmit DPU of a faulty regular channel is switched to the error correcting encoder of a standby channel.

22 citations


Patent
Mitsurou Ohuchi1
08 May 1987
TL;DR: In this paper, a plurality of bits representing the image to be processed are applied in word format to gate circuits which selectively pass certain ones of the bits in each received word in accordance with a selected shrinking or enlargement scale factor.
Abstract: An image processing apparatus capable of shrinking or enlarging images. A plurality of bits representing the image to be processed are applied in word format to a plurality of gate circuits which selectively pass certain ones of the bits in each received word in accordance with a selected shrinking or enlargement scale factor. For shrinking the gate circuits pass selected ones of the bits forming each word, but less than the number of bits in a received word. For enlargement the gate circuits pass the full number of bits in each word, but cause the bits constituting a word at the output of the gate circuits to contain two or more bits of the same content as that of at least the first bit of each input word. Packing apparatus is provided to pack bits at the output of the gate circuits representing a shrunk image into words having a number of bits equal to that of input words to the gate circuits.

20 citations


Patent
08 Jun 1987
TL;DR: In this article, the error signal is divided into a first digital signal having upper bits of data having a predetermined bit number and a second digital signal with the remaining lower bits of the data.
Abstract: A motor rotation control apparatus employs a comb filter circuit operable to filter out a signal component and its higher harmonics. An error signal indicative of an error between actual and target conditions of rotation of the motor is applied to the comb filter circuit after its DC component is removed. The filtered signal and the error signal are added in a circuit which produces a control signal used to control the motor rotation. In another aspect of the invention, the error signal is divided into a first digital signal having upper bits of data having a predetermined bit number and a second digital signal having the remaining lower bits of data. The lower bits of data are delayed a predetermined time and added to the error signal to compensate for lower bits of data which may be ignored in a digital-to-analog converter operable, with a limited bit number, to provide a control analog signal used to control the motor rotation.

16 citations


Patent
09 Nov 1987
TL;DR: In this article, a video signal processing system is described in which a characteristic of individual picture points is provided to an accuracy of m binary bits but conveyed by n bits, where n is less than m. The value of a lower order bit of the n bit signal is switched to cause, for any one picture point, either a value above or a value below the original value.
Abstract: A video signal processing system is described in which a characteristic of individual picture points is provided to an accuracy of m binary bits but conveyed by n bits, where n is less than m. The value of a lower order bit of the n bit signal is switched to cause said binary value to represent, for any one picture point, either a value above or a value below the original value. The new values are distributed without order among the picture points with a probability dependent upon the value of the (m-n) lowest order bits of the desired value.

15 citations


Patent
03 Mar 1987
TL;DR: In this paper, the authors describe the use of a parallel-series converter to inject "idle" bits into the bit stream conveyed to the space switching stage by means of a series-parallel converter at the output of the space-switching stage.
Abstract: The invention relates to a broadband space switching network and to a parallel-series converter and to a series-parallel converter in combination with such a space switching network. The cross-­points of the space switching network are set once per n-bit work. So as to find the time required therefor each word contains (n -n₁) "idle" bits, n₁ representing the number of information bits. During the time in which the "idle" bits are transmitted the space switching network is switched to the desired new state. The parallel-series converter, which is also required for other reasons, is used to inject "idle" bits into the bit stream conveyed to the space switching stage. The "idle" bits are removed again by means of a series-parallel converter at the output of the space switching stage.

12 citations


Patent
10 Sep 1987
TL;DR: In this article, a data transmission system includes a data transmitter for transmitting either data bits or a sequence of N alarm bits in a first binary state, and the receiver performs the reciprocal operation of the data transmitter.
Abstract: The data transmission system includes a data transmitter for transmitting either data bits or a sequence of N alarm bits in a first binary state The transmitter includes a decode circuit (16) providing a detection signal each time that, in a data bit stream, a sequence of n bits in the first binary state has been loaded in a shift register (14), a XOR circuit (18) modifying the binary state of the bit following the sequence of n bits in response to the detection signal provided by the decode circuit (16), thereby providing a modified data bit stream on the transmit line (20), the number n being chosen so that no modified data bit stream can be formed of N bits in the first binary state which could be confused with the sequence of N alarm bits On the reception side, the data receiver performs the reciprocal operation of the data transmitter

11 citations


Patent
Michio Shimada1
21 Sep 1987
TL;DR: In this article, an encoder replica of a decoder for an input code sequence which corresponds to a code symbol sequence comprising an information symbol sequence and a redundancy bit sequence is presented.
Abstract: In an encoder replica of a decoder for an input code sequence which corresponds to a code symbol sequence comprising an information symbol sequence and a redundancy bit sequence, a one-bit memory (46) successively memorizes consecutive bits of the input code sequence as memorized bits. An output circuit (62) delivers replica output bits in bit series to a sequential decode controller (43) in response to the memorized bits. In response to the memorized bits and a control signal produced by the controller in response to the input code sequence and the replica output bits, the encoder replica decodes the input code sequence into a reproduction of the information symbol sequence. Preferably, the output circuit is controlled by a position counter (64) giving separate indication of bits corresponding in the input code sequence to the information symbol sequence and of bits corresponding in the input code sequence to the redundancy bit sequence. More preferably, a synchronism shift counter corrects the saparate indication in consideration of a shift in synchronism of the separate indication relative to the input code sequence.

10 citations


Patent
27 May 1987
TL;DR: In this paper, an analog-to-digital converter (ADC) is controlled in a manner to increase its precision by applying a stepped or dither voltage signal to the other summing means input during each analog signal sampling period of the ADC.
Abstract: An analog-to-digital converter (ADC) controlled in a manner to increase its precision. The signal to be digitized is one input to an analog signal summing means whose output is the input to the ADC. A stepped or dither voltage signal is applied to the other summing means input during each analog signal sampling period of the ADC. The dither voltage steps are equal to the voltage equivalent of one ADC count plus 1/N where N is the number of steps per ADC count chosen to obtain a desired degree of precision in the digital signals that are output by the ADC. The dither voltage step that is combined with the current analog signal sample in the summing means amounts to displacing the sample in steps within each count of the ADC. The ADC converts each combined signal during a sampling interval to a succession of binary digital values which are summed. The result of the summation is a binary number having a value that corresponds more precisely to the true value of the analog signal samples than would be the case if they were converted directly by the ADC.

Patent
10 Jun 1987
TL;DR: In this article, an error signal (DS) indicative of an error between actual and target conditions of rotation of the motor is applied to the comb filter circuit (10) after a direct current component thereof is removed.
Abstract: A motor rotation control apparatus employs a comb filter circuit (10) to filter out a signal component and its higher harmonics. An error signal (DS) indicative of an error between actual and target conditions of rotation of the motor is applied to the comb filter circuit (10) after a direct current component thereof is removed. The filtered signal and the error signal are added in a circuit (90) which produces a control signal used to control rotation of the motor (50). Predetermined successive portions (samples) of the error signal may each be divided into a first digital signal portion having a predetermined number of upper bits of data and a second digital signal portion having the remaining lower bits of data. The lower bits are delayed a predetermined time and added to the error signal to compensate for lower bits of data which may be ignored in a digital-­to-analog converter, operable on a limited number of bits, to provide an analog control signal used to control rotation of the motor.

Patent
18 Aug 1987
TL;DR: In this article, a method for compressing and de-compressing binary decision data by arithmetic coding and decoding is presented, wherein the estimated probability Qe of the less probable of the two decision events, or outcomes, adapts as decisions are successively encoded.
Abstract: Apparatus and method for compressing and de-compressing binary decision data by arithmetic coding and decoding wherein the estimated probability Qe of the less probable of the two decision events, or outcomes, adapts as decisions are successively encoded. To facilitate coding computations, an augend value A for the current number line interval is held to approximate one by renormalizing A whenever it becomes less than a prescribed minimum AMIN. When A is renormalized, the value of Qe is up-dated. The renormalization of A and up-dating of Qe are preferably based on a single-bit test. Also, each Qe value is preferably specified as a 12-bit value having the least significant bit set to 1 and having no more than four other bits set to 1. The number of Qe values in the 1/4 to 1/2 probability range is enhanced to improve coding efficiency. A decision coding parameter of preferably six bits indicates the sense of the more probable symbol (MPS) in one bit and identifies a corresponding Qe value with the remaining five bits. In addition to probability adaptation, the present invention discloses an allocation of bits in a code stream register in which preferably two spacer bits are inserted between a next byte portion (which contains a byte of data en route to a buffer) and a fractional portion which may be involved in further computation. With the two spacer bits, any code greater than or equal to Hex 'CO' which follows a Hex 'FF byte is illegal for data and therefore provides for an escape from the code stream. The two spacer bits also reduce the number of stuff bits inserted to account for carry or borrow propagation. Encoding and decoding can be performed interchangeably by hardware or software which feature differing coding conventions.

Patent
01 Dec 1987
TL;DR: In this article, a digital filtering circuit for determining which value is in the k position of an increasing or decreasing ordered sequence of n binary digital values received out of order by the filter is described.
Abstract: The invention relates to a digital filtering circuit for determining which value is in the k position of an increasing or decreasing ordered sequence of n binary digital values received out of order by the filter. It is determined whether there are k or more than k zeroed high-order bits in the n high-order bits of the n values to be processed, and a possible modification of the other bits is deduced therefrom; then, the same determination is begun again on the bits of immediately lower rank, taking into account bits such as have or have not been modified; a modification is made again depending on the result of the new determination; and so on down to the lowest rank. The sought-after value is given in binary form by the signals representing the results of these successive tests. This filter is particularly suited to real-time filtering of television picture signals.

Patent
Inamasu Nami1
20 Oct 1987
TL;DR: In this article, a digital signal is divided into two groups of upper bits and lower bits which are converted to a first and second analog signals respectively, and the two signals are added to produce an analog signal after the second analog signal is attenuated by an attenuating factor depending on the number of the lower bits.
Abstract: In a digital to analog converter, a digital signal is divided into two groups of upper bits and lower bits which are converted to a first and second analog signals respectively. The digital analog converter comprises means for adding a predetermined value of a signal to the lower bits. A carry signal in the addition of the predetermined value is applied to the upper bits. The upper and lower bits of the digital signal thus controlled are converted to a frist and second analog signals separately. Thereafter, the two signal are added to produce an analog signal after the second analog signal is attenuated by an attenuating factor depending on the number of the lower bits.

Patent
Wan-On Chan1
09 May 1987
TL;DR: In this paper, the voltage level of the input signal is shifted by a variety of amounts therewith a wider range of voltages fitting into the available dynamic range of the converter.
Abstract: For enhancing the resolution of an analog to digital converter the voltage level of the input signal is shifted by a variety of amounts therewith a wider range of voltages fitting into the available dynamic range of the converter. The amount of shift selected may also be used to add additional bits to the digital signal.

Patent
21 Jul 1987
TL;DR: In this paper, the circuit for detecting synchronism in a digital broadcast receiver comprises series-parallel converters (20,21) receiving respective synchronisation word outputs (25,31) of a 4-phase PSK demodulator; conversion means (26-31; 33-37) for making all the seriesparallel converter outputs high level; and 1st and 2nd AND gates (38,39) which receive series-PARC output and whose outputs are supplied to an OR gate (40).
Abstract: of EP0255840The circuit for detecting synchronism in a digital broadcast receiver comprises series-parallel converters (20,21) receiving respective synchronisation word outputs (25,31) of a 4-phase PSK demodulator; conversion means (26-31; 33-37) for making all the series-parallel converter outputs high level; and 1st and 2nd AND gates (38,39) which receive series-parallel converter outputs and whose outputs are supplied to an OR gate (40). Input to the 1st AND gate is a combination of the odd-numbered bits in the output of one series-parallel converter and the even-numbered bits in the output of the other series-parallel converter, while the 2nd AND gate's input consists of the other output bits of the converters.

Patent
Aichelmann Frederick John1
08 Sep 1987
TL;DR: In this paper, a circuit for quickly determining if all data bits in an ECC word are correct and/or for detecting failures in an error detection syndrome generation path is presented.
Abstract: A circuit for quickly determining if all of the data bits in an ECC word are correct and/or for detecting failures in an error detection syndrome generation path in an ECC circuit, where the ECC circuit utilizes an error correction code with two diagonal quadrants in the code matrix composed entirely of columns which have an even number of ones, and with the other two quadrants composed entirely of columns which have an odd number of ones. In one embodiment, the circuit comprises for generating a parity bit, P k , for each of K data fields in the ECC word; for comparing logical combinations of these parity bits to logical combinations of the memory check bits, C j , to form H bits; and for logically combining these H bits to form a D bit. This D bit may be compared to the binary (non carry) sum of the syndrome bits to detect syndrome generation path failures. This D bit may also be used to determine if the data bits in an ECC word are correct, a number of cycles before the completion of the normal ECC operation.

Proceedings ArticleDOI
Choon Lee1, Morton Nadler1
13 Oct 1987
TL;DR: In the previous paper, the techniques of dual-mode coding were introduced and one of the techniques uses the two-dimensional delta modulation to code the image pixels using the Graham's predictor and the normal predictor which sends the direction bits.
Abstract: In the previous paper, the techniques of dual -mode codingwere introduced. One of the techniques uses the two - dimensional delta modulation to code the image pixels. In this scheme, the predictor is switched Latween the Graham'spredictor and the normal predictor which sends the directionbits. The bit rate is the lowest of the considered systems. Inthis paper, the channel coding of the system is considered. Especially in coding the difference bits, several methods were studied including the ordering of the bits according tothe two -dimensional statistics of the difference bit map. Thewindow for the predictor of the difference bits was designedto maximize the coding efficiency. For a variety of imagestested in this paper, the bit rates for the difference bits werein the range 0.6717 - 0.8774 bits /pixel which are about 11 to28 percent less than those of the one -dimensional run -lengthcoded bits. 1. INTRODUCTION The research on the dual -mode predictive coding systems was carried out by Lee et al'.

Patent
31 Aug 1987
TL;DR: In this article, the authors propose a monitoring arrangement that periodically and repetitively provides a test bit which can be read into or out of the memory arrangement in parallel to the data signal bits.
Abstract: A circuit arrangement includes a memory arrangement in which data signal bits forming the data signals can be read in at read-in times determined by a first clock pulse train and from which these data signal bits can be read out at read-out times determined by a second clock pulse train. A monitoring arrangement periodically and repetitively provides a test bit which can be read into or as the case may be out of the memory arrangements in parallel to the data signal bits. At its initialization, this monitoring arrangement enables the reading out of data signal bits previously entered in the memory arrangement with a delay, such that thereafter a predetermined phase relationship exists between test bits read into and read out of the memory arrangement. The monitoring arrangement provides a control signal which disables the memory arrangement lilmited in time with regard to the reading out of data signal bits and test bits when a defined predetermined change in this phase relationship is exceeded. Through such disabling, the defined phase relationship between test bits read in and read out is at least substantially reestablished.