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Showing papers on "Effective number of bits published in 1989"


Patent
23 Jun 1989
TL;DR: In this article, a convolutional encoder adds n number of bits so that the total number of parallel bits is m+n, which is applied to the mapping circuit, and the coding gain is improved since the number of levels of the QAM signal is not increased although the bandwidth of the signal is a little increased.
Abstract: TITLE OF THE INVENTION Coded Modulation Communication System ABSTRACT OF THE DISCLOSURE In Trellis coded modulation system in which an input digital signal in parallel form is encoded by a convolutional encoder which adds an additional bit to the input digital signal for error correction purpose, and a mapping circuit designates amplitude and phase for each symbol for QAM signal, the number of parallel bits at output of said convolutional encoder is the same as the number of parallel bits of an input digital signal. An input digital signal is first rate converted so that m+n bits in every T period is converted to m bits in every T' period, where T'=(m/(m+n))?T. The convolutional encoder adds n number of bits so that the total number of parallel bits is m+n, which is applied to the mapping circuit. In a receive side, a receive signal having m+n bits in every T' period is decoded through an error correction decoder which provides m bits in every T' period, then, the decoded signal is rate converted to m+n bits in every T period. So, the number of parallel bits does not increase in spite of convolutional encoding, but a transmission rate is a little increased. The coding gain in the present invention is improved since the number of levels of the QAM signal is not increased although the bandwidth of the signal is a little increased because of the higher clock rate.

24 citations


Patent
24 Feb 1989
TL;DR: In this paper, a comparator/multiplexer section compares the comparison signals against ground, selects one of the comparison signal and produces a code, and an amplifier amplifies the selected comparison signal.
Abstract: This multi-flash analog-to-digital converter (ADC), in particular dual flash ADC, has extremely high speed and resolution. The final resolution of a comparator/multiplexer section can be effectively doubled. For instance, a 16-bit ADC can employ 300 rather than 255 comparators. A monolithic integration can be accomplished. A resistive network is coupled to a current source and to a reference signal for providing a plurality of comparison signals. A comparator/multiplexer section compares the comparison signals against ground, selects one of the comparison signals and produces a code. An amplifier amplifies the selected comparison signal. A switch provides the reference signal in response to the ADC input signal and subsequently in response to the amplifier output signal. Two codes are encoded and converted into the output code of the ADC.

23 citations


Proceedings ArticleDOI
E. Seifert1, A. Nauda1
01 Jun 1989
TL;DR: A technique for improving the dynamic range of analog-to-digital converters (ADCs) by summing outputs of several parallel N-bit ADCs to reduce the uncorrelated excess noise introduced by each ADC.
Abstract: A technique for improving the dynamic range of analog-to-digital converters (ADCs) is presented. The technique consists of summing outputs of several parallel N-bit ADCs to reduce the uncorrelated excess noise introduced by each ADC. This increases the number of effective bits of resolution and is most useful to regain bits lost after dithering to reduce spurious harmonics for spectral analysis applications. The sensitivity of this approach to uncertainties in component gain and delay is discussed. >

22 citations


Patent
31 Mar 1989
TL;DR: In this paper, a data packer receives n-bit wide parallel data words, and it outputs mbit wide packed parallel data word, where n is a variable and may change during the operation, and m is a fixed integer.
Abstract: The data packer receives n-bit wide parallel data words, and it outputs m-bit wide packed parallel data words, where n is a variable and may change during the operation, and m is a fixed integer. The input data words are applied to a bit shifter and therefrom to a data output circuit where they are stored until the necessary m bits are obtained. In the preferred embodiment a control circuit which comprises an adder, receives information indicating the number of valid data bits in each input word, and it provides a running sum of the number of received valid data bits. When the number of bits in an input word is equal to or greater than m, the control circuit provides a first control signal which occurs simultaneously with an m-bit wide packed parallel output word provided by the output circuit. Any number of input bits which is less than m is added to a remainder of a previous sum which is also less than m. When the thusly obtained sum is equal to or greater than m, a second control signal is provided which also occurs simultaneously with an m-bit wide packed word provided by the output circuit. The control circuit applies the running sum as a third control signal to the bit shifter, effecting shift of the next received data word by a number of bit positions corresponding to that sum. The number indicated by the third control signal also corresponds to the number of bits currently stored in the output circuit.

22 citations


Journal ArticleDOI
TL;DR: GaAs ICs for high-speed, 6-b, 1G-sample/s (Gs/s) data acquisition are under development, using a low-cost conventional D-MESFET technology, and second-generation analog-to-digital converter (ADC) building blocks have been made.
Abstract: GaAs ICs for high-speed, 6-b, 1G-sample/s (Gs/s) data acquisition are under development, using a low-cost conventional D-MESFET technology. First-generation sample-and-holds (S/Hs) and comparators are currently being sampled to customers. Diode-bridge and FET-switch S/Hs have been compared. Best performances have been achieved with diode-bridge switches: 1 ns and 6 bits. Comparators provide 6-b sensitivity at 1 GHz, but require offset adjustments. Second-generation analog-to-digital converter (ADC) building blocks have been made. Performances and applications of resulting circuits as well as advanced ADC design criteria are discussed, with special attention to yield. First results on a 4-b ADC are presented. >

14 citations


Patent
01 May 1989
TL;DR: In this article, a method of comparing two binary quantities, which includes comparing corresponding bits of each of the binary quantities and generating comparison signals to indicate equality and inequality of corresponding bit of the quantities, is presented.
Abstract: A method of comparing two binary quantities, which includes comparing corresponding bits of each of the binary quantities and generating comparison signals to indicate equality and inequality of corresponding bits of the quantities. The comparison signals are transferred to a transfer line with the signals being arranged in order on the transfer line from the signal corresponding to the most significant bits to that corresponding to the least significant bits. A selected number of the comparison signals are coupled in order of priority from that corresponding to the most significant bits to that corresponding to the least significant bits, to an output EQUALS line in response to a plurality of decode signals.

13 citations


Patent
25 Apr 1989
TL;DR: In this paper, a plural channel indirect digital to analog converter is described, where words containing address bits and data bits are received on an input and entered into a specific one of the converter channels under control of the address bits of the word.
Abstract: A plural channel indirect digital to analog converter. Words containing address bits and data bits are received on an input and entered into a specific one of the converter channels under control of the address bits of the word. The data bits are applied to a binary rate multiplier of the channel which generates a pulse modulated output signal representing the binary value of the received data bits. The pulse modulated output signal is applied to an associated filter which converts the pulse modulated signal to an analog output signal whose amplitude represents the binary value of the received data bits. Gating circuitry ensures that each output pulse is of a precisely controlled pulse width. One of the converter channels is used to calibrate the output level of the filters. The number of data bits applied to the different channels may need not be the same and may vary in number from a minimum of 1 to a maximum of m.

12 citations


Patent
06 Feb 1989
TL;DR: In this paper, the main stage of an electronic circuit contains a main stage that produces a digital code consisting of a plurality of bits (B₀ - B M-1 ) that make binary transitions as a function of an input parameter (V I ).
Abstract: An electronic circuit contains a main stage (10 and 12) that produces a digital code consisting of a plurali­ ty of bits (B₀ - B M-1 ) that make binary transitions as a function of an input parameter (V I ). A synchronization stage (14 and 16) synchronizes transitions of bits (B₀ - B K-1 ) in one part of the code with corresponding transitions of bits (B K - B M-1 ) in another part. When the input parameter is in transition regions where bits in the first-mentioned part of the code could go to wrong values, the synchronization stage suitably replaces the values of bits in the first part with information based on bits in the other part.

11 citations


Patent
04 Apr 1989
TL;DR: In this article, a word serial multiplier includes a first circuit loop for loading a parallel-bit multiplier, and in response to a clock signal sequentially produces a gate signal corresponding to a sequence of bits of the multiplier sample in descending order of significance.
Abstract: A word serial multiplier includes a first circuit loop for loading a parallel-bit multiplier, and in response to a clock signal sequentially produces a gate signal corresponding to a sequence of bits of the multiplier sample in descending order of significance A second circuit loop loads a multiplicand sample and in response to the clock signal successively divides the multiplicand sample by the factor two The more significant bits, exclusive of the least significant bit, of the divided multiplicand sample are coupled to a gating circuit The gating circuit passes the more significant bits to the input of an accumulator if the corresponding bits of the gate signal exhibit a predetermined state After a number of cycles of the clock signal, corresponding to the number of bits m of the multiplier sample, the accumulator produces a scaled product equal to the muliplicand times the multiplier times the scale factor of 2 - (m-1)

11 citations


Patent
03 Jan 1989
TL;DR: In this paper, a receiver for receiving and decoding a baseband multilevel signal into a digital data signal, and A/D converter produces in addition to the decoded data bits a "soft" bit, which inherently indicates the error polarity of the baseband signal.
Abstract: In a receiver for receiving and decoding a baseband multilevel signal into a digital data signal, and A/D converter produces in addition to the decoded data bits a "soft" bit, which inherently indicates the error polarity of the baseband signal. The soft bits are binary added to the most significant data bits to produce a sum bit. The sum bits are integrated, and the integral is used in a feedback loop to control the baseband signal amplitiude.

10 citations


Patent
23 Oct 1989
TL;DR: In this article, the S-bit lower-bit-output-approximate data are set such that, supposing a level change of the added analog signal with respect to a change of an LSB of the upper M bits being ΔL, a minimum step increase of the digital signal of lower N bits causes a level of the add analog signal to increase by about ΔL/2 N.
Abstract: A digital/analog converting device comprises a first digital/analog converter for converting upper M bits of an input digital signal into a first analog signal; a memory for receiving, as address data, at least a digital signal of lower N bits of the input digital signal to output lower-bit-output-approximate data of S (S>N) bits in response to the address data; a second digital/analog converter for converting digital data at least including the S-bit lower-bit-output-approximate data into a second analog signal; and an analog adder for outputting an added analog signal obtained by adding the first and second analog signals at a predetermined ratio. The S-bit lower-bit-output-approximate data are set such that, supposing a level change of the added analog signal with respect to a change of an LSB of the upper M bits being ΔL, a minimum step increase of the digital signal of lower N bits causes a level of the added analog signal to increase by about ΔL/2 N .

Patent
24 Jul 1989
TL;DR: In this paper, the serial binary data stream to be transmitted is supplied to a means for rate matching and for serial-to-parallel conversion wherein, first, the data rate is increased to the transmission rate upon formation of free locations for the acceptance of redundancy bits and, second, a corresponding plurality of parallel data streams are generated from the serial data stream, respectively one half of said parallel data stream forming the I-channel and the other half forming the Q-channel.
Abstract: For the employment of an FEC method in systems of a variety of types, the serial binary data stream to be transmitted is supplied to a means for rate matching and for serial-to-parallel conversion wherein, first, the data rate is increased to the transmission rate upon formation of free locations for the acceptance of redundancy bits and, second, a corresponding plurality of parallel data streams are generated from the serial data stream, respectively one half of said parallel data streams forming the I-channel and the other half forming the Q-channel. The redundancy locations lie in the least significant bits of the I-channel and Q-channel. The more significant bits of the I-channel and the Q-channel directly control the appertaining inputs of a quadrature modulator, whereas the least significant bit is supplied to the appertaining input via a respective multiplexer. In addition, the least significant bit of the I-channel and the Q-channel is respectively supplied to a coder, each of these coders considering a defined plurality of incoming bits; and generating one or more redundancy bits therefrom in accord with the coding rule of a specific underlaid code. These redundancy bits are inserted with the assistance of the multiplexers at locations in the I-channel and Q-channel, that are provided for this purpose.

Patent
04 Apr 1989
TL;DR: In this article, the most significant bits are used to define first and second ranges where the first range defines a set of data bits used for indirect addressing of traffic information and the second range can be used in a direct addressing mode to substitute the lesser significant bits of those stored in the first memory in place of traffic memory data bits.
Abstract: Typically time multiplexed switches use an indirect addressing scheme where a set of data bits in a first addressable memory define addresses in a second addressable memory as part of a read function to time switch an output data stream previously stored in the second memory. In a situtation where there are less channels of traffic than there are potential addresses as defined by the number of bits stored in the first memory, the most significant bits can be used to define first and second ranges where the first range defines a set of data bits used for indirect addressing of traffic information and the second range can be used in a direct addressing mode to substitute the lesser significant bits of those stored in the first memory in place of traffic memory data bits when the stored most significant bits are detected to define the second range of data bits. Such an approach considerably simplifies the circuitry required to perform this additional multiplexing operation of signal data into the traffic data stream.

Patent
26 May 1989
TL;DR: In this paper, a comparative judging circuit, a polarity inversion circuit, and a signal generation circuit are presented to reduce the number of output signals that change simultaneously and to prevent the malfunction of a digital circuit by transmitting the signal representing data with either positive or negative polarity with the data to be transmitted.
Abstract: PURPOSE: To reduce the number of output signals that change simultaneously and to prevent the malfunction of a digital circuit by transmitting the signal representing data with either positive polarity or negative polarity with the data to be transmitted. CONSTITUTION: A comparative judging circuit 17, a polarity inversion circuit 18, a polarity signal generation circuit 32, and a selector 19, etc., are provided. The number of change bits of the data desired to output is detected, and it is judged whether or not the number of change bits exceeds the half of the number of all bits, and regular data is outputted when the former is less than the latter, and inverted data is outputted when the former exceeds the latter. By executing such processing at every data to be outputted, the number of change bits that change simultaneously on a bus can be suppressed to the one less than the half of the number of all bits. At a reception side, since it is necessary to recognize the polarity of inputted data, one signal line 26 is added in addition to a signal line for data carrying. In such a way, the power consumption in the digital circuit can be reduced, and also, unrequired electromagnetic wave radiation can be reduced, and the malfunction can be prevented. COPYRIGHT: (C)1990,JPO&Japio

Proceedings ArticleDOI
25 Apr 1989
TL;DR: A 1-megasamples/s 16-bit analog-to-digital converter (ADC) that uses a subranging conversion technique and high accuracy at a 1-MHz conversion rate is obtained with novel circuits developed for a track-and-hold device, a residue amplifier, and a digital-to -analog converter.
Abstract: The author describes a 1-megasamples/s 16-bit analog-to-digital converter (ADC) that uses a subranging conversion technique. High accuracy at a 1-MHz conversion rate is obtained with novel circuits developed for a track-and-hold device, a residue amplifier, and a digital-to-analog converter. Design aspects of these key functional circuits are presented. A prototype ADC was fabricated on a printed-circuit board and tested. Curve-fit test results show that up to 100 kHz, the effective bits decrease to 14 bits due to wideband noise. However, signal bandwidth is commonly restricted in spectrum analysis, so a dynamic range of over 96 dB can be obtained. >

Patent
31 Jul 1989
TL;DR: In this article, the serial binary data stream to be transmitted is supplied to a device for rate adaptation and serial/parallel conversion, in which, on the one hand, the data rate is increased to the transmission rate, forming free spaces for accommodating redundancy bits, and on the other hand, from the serial data stream a corresponding number of parallel data streams is generated, one half of which forms the I and Q channels, respectively.
Abstract: For using such a FEC method in systems of the most varied type, the invention provides that the serial binary data stream to be transmitted is supplied to a device for rate adaptation and serial/parallel conversion, in which, on the one hand, the data rate is increased to the transmission rate, forming free spaces for accommodating redundancy bits, and, on the other hand, from the serial data stream a corresponding number of parallel data streams is generated, one half of which in each case forms the I and Q channel, respectively. The redundancy spaces in this arrangement are located in the least-significant bits of I and Q channel. The higher-significance bits of I and Q channel directly control the associated inputs of a quadrature modulator, while the least-significant bit is supplied to the relevant input in each case via a multiplexer. In addition, the least-significant bit of I amd Q channel is in each case supplied to a coder, each of which looks at a particular number of incoming bits and from these generates one or several redundancy bits in accordance with the coding rule of a particular basic code. These bits are inserted into the places provided for this purpose in the I and Q channel, respectively, with the aid of the two multiplexers. … …

Proceedings ArticleDOI
S. Ramet1
15 Feb 1989
TL;DR: The author describes a 13-bit, 160-kHz differential ADC (analog-to-digital converter), and an 80-kHz version, both including a reference circuit delivering two voltages that are symmetrical with respect to the power supply midpoint.
Abstract: The author describes a 13-bit, 160-kHz differential ADC (analog-to-digital converter), and an 80-kHz version, both including a reference circuit delivering two voltages that are symmetrical with respect to the power supply midpoint. These circuits are implemented in the 1.2- mu m CMOS double-metal process using an extra n+ diffusion to accommodate poly/n+ capacitors. Starting from the k-bit linearity requirement for the capacitor array and considering previous results, the bits were partitioned into P=4 bits for the resistor-string and K=9 bits for the capacitor array. The fast Fourier transform (FFT) result is shown for a 5-kHz sine-wave full-scale input sampled at 160 kHz. The performance of the circuit is summarized. >

Proceedings ArticleDOI
15 May 1989
TL;DR: An 11-bit, audio-speed analog-to-digital (A/D) converter for echo cancellation applications, which appears to consume the smallest chip area of any comparable converter, has been developed.
Abstract: An 11-bit, audio-speed analog-to-digital (A/D) converter for echo cancellation applications, which appears to consume the smallest chip area of any comparable converter, has been developed. It digitizes an analog input using the multislope integration technique, and requires one external capacitor. The DC and dynamic performance of the A/D converter were measured. The measured error plot indicates an integral nonlinearity of p2 LSB (least significant bit) at 12 bits with no missing codes. A differential nonlinearity of p0.5 LSB at 12 bits was measured using a statistical method. An S/N (signal-to-noise) versus input level measurement, obtained from the spectrum of the digitized output, indicates the effective dynamic linearity of the converter to be between 10 and 11 bits. The bandwidth is set by the sample-and-hold circuit

Proceedings ArticleDOI
25 Apr 1989
TL;DR: An analog-to-digital converter consisting of a switched-capacitor integrator, comparator, and control circuit is presented and error analysis shows that a conversion accuracy higher than 12 bits can be expected from a CMOS monolithic realization.
Abstract: An analog-to-digital (A/D) converter consisting of a switched-capacitor integrator, comparator, and control circuit is presented. The conversion process consists of voltage-to-frequency (V/F) conversion to determine the upper M bits of an N-bit representation of an analog input voltage and the subsequent voltage-to-time (V/T) conversion to determine the remaining lower N-M bits. The total clock cycle required for N-bit resolution is 2/sup M/+2/sup N-M/ at most. The circuits for the V/F and V/T conversion share most of the components and thus the converter can be implemented with the minimum component count. Error analysis shows that a conversion accuracy higher than 12 bits can be expected from its CMOS monolithic realization. Prototype converters built using discrete components have confirmed the principles of operation. >

Proceedings ArticleDOI
01 Nov 1989
TL;DR: A multistage vector quantization technique applied to the transform coefficients, where the effective number of bits assigned to each coefficient is proportional to the coefficient variance, which is well suited for progressive image transmission.
Abstract: In this paper, we introduce a multistage vector quantization technique (MVQ-OBA) applied to the transform coefficients, where the effective number of bits assigned to each coefficient is proportional to the coefficient variance. An optimal bit allocation map for a given bit rate, {Bij}, is first found based on the variances of the transform coefficients. The optimal bit allocation map, {Bij} is then sliced into a set of bit allocation planes {Bk,ij, k = 0,1,...} by applying a set of thresholds {Tk, k = 0, 1,...}. Here, Bk,ij indicates the number of bits assigned to coefficient (i, j) at stage k. The transformed image is then vector quantized on a stage-by-stage basis where, at each stage k, only the (residual error) coefficients assigned a non-zero number of bits are combined into vectors and vector quantized with a codebook of size 2∑i,jBk,ij Since only part of the coefficients are included into vectors and a relatively small codebook is used at each stage, the overhead required for transmitting the codebook is significantly reduced. Furthermore, as MVQ-OBA operates in a multistage manner where the information transmitted up to each stage corresponds to an approximation of the image, it is well suited for progressive image transmission.

Proceedings ArticleDOI
23 May 1989
TL;DR: An ADC (analog/digital converter) architecture based on a residue number system (RNS) and multiple folding of the input signal is described, which results in a low-cost high-speed ADC suitable for consumer video applications.
Abstract: An ADC (analog/digital converter) architecture based on a residue number system (RNS) and multiple folding of the input signal is described. The number of comparators used is equal to the sum of moduli for obtaining the dynamic range desired. An error correction circuit and overflow detection are possible. RNS ADC makes use of an analog preprocessing stage for multiple folding of the input signal before flash conversion to reduce the hardware and to achieve high-speed operation. The main drawback of the architecture is that a residue code that does not change gradually, such as the Gray code, and error correction are necessary to avoid large errors. Higher resolution is possible without much increase in hardware. It is concluded that this reduced hardware architecture results in a low-cost high-speed ADC suitable for consumer video applications. >

Patent
06 Feb 1989
TL;DR: In this paper, the effective bits of a variable length code as an input and to simplify a circuit by adding more than one discriminatable additional bits after the effective data of a word at a different bit length, making the lengths fixed, and detecting and eliminating the additional bits from the fixed length encoded word.
Abstract: PURPOSE: To make unnecessary the effective bits of a variable length code as an input and to simplify a circuit by adding more than one discriminatable additional bits after the effective data of a variable length encoded word at a different bit length, making the lengths fixed, and detecting and eliminating the additional bits from the fixed length encoded word. CONSTITUTION: When (n)-bit variable length codes are inputted from variable length code input terminals DI1 to DIn, the bits of an input shift register 14 are shifted by one to a high-order side at the timing of a clock 2. A comparing circuit 15 inputs one discriminatable additional bit or more other than the highest-order bit of the input shift register 14 in units of a clock, and the circuit 15 detects a pattern. Further an output shift register 17 shifts the bits by one to the high-order side, and simultaneously inputs one bit outputted from the input shift register 14 to the lowest-order bit. A counter 16 counts the bits until the data of the output shift register 17 amount to the (n) bits, and when they amount to the (n) bits, the data of the output shift register 17 are outputted from output terminals DO1 DOn in parallel. COPYRIGHT: (C)1990,JPO&Japio

01 Jan 1989
TL;DR: The effectiveness of differ- ent classes of arithmetic codes for concurrent error detec- tion in systolic arrays is investigated by analyzing the implications of these codes on the size of the multiplier circuits.
Abstract: This paper addresses the problem of detection and iden- tification of a faulty processing element in a systolic array. A method for designing processing elements with concurrent error detection is presented. The I RAN(,,, code ( 11 is shown to be an effective code for encoding the operands in a systolic array. It is shown that the 1 g3N I,+, code is equivalent to a residue code with the check and information bits interchanged, for odd number of information bits. This allows arithmetic to be performed separately on the information and check bits while the output can be checked by an ANchecker. An architecture and rules for designing a self-checking processing element (PE) for sys- tolic arrays are presented. Both redundancy and extra delay of the self- checking PE are shown to be low. This paper first investigates the effectiveness of differ- ent classes of arithmetic codes for concurrent error detec- tion in systolic arrays by analyzing the implications of these codes on the size of the multiplier circuits. The 1 @NIM code ( 13 is shown to be an effective code for en- coding the operands in a systolic array. Here, (gANIM denotes gAN modulo M. In Section 111, multiplication is defined for the I gAN code. It is shown that the 1 g3N IM code is equivalent to a residue code with the check and information bits interchanged, for an odd number of in- formation bits. When the number of information bits is even, the check bits can easily be obtained from the res- idue of the information bits. Using this interesting prop- erty, an architecture and rules for designing a self-check- ing processing element (PE) for systolic arrays are presented in Section V. A parallel multiplier array design that performs modulo 2k - 1 multiplication is also devel- oped. Pepnnance of the self-checking PE is evaluated based on a gate level design. It is shown that the redun- dancy is very low, especially for larger wordlengths. The delay is due to the checkers only since the circuits per- forming arithmetic on the check bits operate in parallel with the circuits performing arithmetic on the information bits. The single stuck-at fault model is used in the dis- cussion of hardware faults. The self-checking design pre- sented detects both permanent and transient faults. The class of systolic arrays where each PE performs the function ci + = ci + ab is addressed. An example of such a systolic array for matrix multiplication is shown in Fig. 1.

Proceedings ArticleDOI
25 Apr 1989
TL;DR: The authors describe a 30-megasamples/s 12-bit analog-to-digital converter (ADC) using a subranging conversion technique and presents a pipelined track-and-hold circuit and a high-speed 5-bit digital- to-analog converter.
Abstract: The authors describe a 30-megasamples/s 12-bit analog-to-digital converter (ADC) using a subranging conversion technique. The key circuits for obtaining high accuracy at a 30-MHz conversion rate are a pipelined track-and-hold circuit and a high-speed 5-bit digital-to-analog converter. These circuit design features are presented. The ADC was fabricated on a printed-circuit board with about 500 surface mounting devices, and utilized for a precision digital oscilloscope. In a curve-fit test, effective bits of better than 10.0 were obtained with up to a 10-MHz input frequency. >

01 Jan 1989
TL;DR: Evaluation of various algorithms used in sinewave parameter estimation and the subsequent effective bit computations for Analog to Digital Converters (ADCs) indicates that the Closed Form Approximation is not as simple as anticipated.
Abstract: The present work deals with the evaluation of various algorithms used in sinewave parameter estimation and the subsequent effective bit computations for Analog to Digital Converters (ADCs). Three algorithms have been investigated in this work. They include the Closed Form Approximation Method, the Three Parameter Fit Method (with known frequency) and the Four Parameter Least Squared Fit Method (with unknown frequency). Both the ADC under consideration as well as the reference data employed in testing the algorithms are simulated in software. The test inputs include pure and corrupted sinewaves. For each case, the degradation in the effective bits for the ADC is observed. Our studies indicate that the Closed Form Approximation is not as simple as anticipated. To obtain even reasonably good estimates, strict phase unwrapping is vital. This is not easily accomplished for unknown sinewaves . The Three Parameter Fit Method gives excellent results when the input frequency is known. Moreover, it is simple and efficient. The only disadvantage is that a correction factor has to be incorporated in the algorithm to compensate for phase estimation errors. The standard Four Parameter Least Squared Fit Method is adequate only for input phase values in the neighborhood of zero degrees. Modifications have been made to this algorithm to deal with arbitrary input phase values. These modifications yield satisfactory results.

Patent
27 Dec 1989
TL;DR: In this paper, the difference between the input analog signal V E and its already digitized part, reconverted into analog form, is disclosed in a cascaded analog-digital converter.
Abstract: In a cascaded analog-digital converter, a first ADC determines the most significant bits. To determine the least significant bits, in a second ADC, it is necessary to assess the difference between the input analog signal V E and its already digitized part, reconverted into analog form. The subtractor/amplifier receives, firstly, the input signal V E which is converted into a current i E and, secondly, the most significant bits on a digital-analog converter. This constitutes a source, capable of being modulated, which gives a current i c . Two parallel-mounted transistors differentiate between the current i c of the source capable of being modulated and the current i E corresponding to the input signal V E , and amplify it. The disclosure is applicable to cascaded ADCs.

Patent
22 Mar 1989
TL;DR: In this paper, the authors proposed to reduce memory capacity and to improve plotting speed by using a circuit constituted of a CRT controller, a frame memory and a shift register as two systems.
Abstract: PURPOSE: To reduce memory capacity and to improve plotting speed by using a circuit constituted of a CRT controller, a frame memory and a shift register as two systems. CONSTITUTION: The circuit constituted of the CRT controller 1, the frame memory 2 and the shift register 3 is used as two systems. This device is provided with a circuit generating a multi-level signal expressing that the display is multi-level display when a scanning line exists at a window part, and uses an output bit number variable type output controller 4 changing the effective number of bits of display data output S3 and the kind of the data by using the multi-level signal and a priority system signal for deciding the order of priority of two systems. In the case the multi-level display and superimposed display are simultaneously executed on a CRT, a necessary storage quantity in substance becomes half and the number of bits per dot becomes half. Thus, the plotting speed becomes double, the memory capacity is reduced, and the plotting speed is improved.

Patent
25 Apr 1989
TL;DR: In this article, it was shown that it is possible to reduce the size of a multiplier circuit by using the overflow of two complementary operations positively in an error correction arithmetic operation in order to reduce power consumption or heat generation, and also to increase computing speed.
Abstract: PURPOSE:To miniaturize a circuit scale as a whole by performing a minimum required arithmetic operation by using the overflow of two complementary operations positively in an error correction arithmetic operation. CONSTITUTION:It is enough to output (i+j-k) bits for inputted bit number (i) and (j) by a multiplier circuit 3, and the bit number of the output word length of a multiplier circuit 5 goes to (i+2j-k) less by (k) bits. Also, in such a case, since an input value X is of (i) bits, the effective number of bits of an output value Y(n+1) goes to the (i) bits, and actually, it is possible to omit the multiplication of the low-order bits of the multiplier circuit 5 to some extent. In other words, the output word length of the multiplier circuit 5 can be set less than (i+2j-k) bits. In such a way, it is possible to reduce the scale of the multiplier circuit 5, and to reduce power consumption or heat generation, and also, to increase computing speed as a whole.

Proceedings ArticleDOI
23 May 1989
TL;DR: The authors present a novel technique for image vector quantization at a bit rate of 0.75 bits/pixel or below with moderately low to very low subjective distortion, which incorporates the multiplicative visual model as part of the distortion measure.
Abstract: The authors present a novel technique for image vector quantization (VQ) at a bit rate of 0.75 bits/pixel or below with moderately low to very low subjective distortion. The encoding scheme incorporates the multiplicative visual model as part of the distortion measure. By modeling the quantization noise as an additive signal-dependent noise process, an optimal pre- and postprocessing system, which minimizes the mean-squared error measured inside the visual model, is derived. The design algorithm for this optimal system is also developed. Using this optimal system, a set of experiments was conducted. Images of surprising quality have been produced at the bit rate of 0.1 bits/pixel with a compression rate of 80:1 relative to a normal 8 bits/pixel original. >

Patent
26 Sep 1989
TL;DR: In this paper, an analog audio signal is retained after a frequency limitation by a scanning holding element (SH) for conversion to an L-bit output value, which forms the higher-valued bits of the output value and is reconverted by a reference D/A converter (RDA).
Abstract: An analog audio signal is retained after a frequency limitation by a scanning holding element (SH) for conversion to an L-bit output value. The scanning signal is converted by a parallel A/D converter (FAD) to a digital reference value with M < L data bits which forms the higher-valued bits of the output value and is reconverted by a reference D/A converter (RDA). This reference signal is subtracted from the scanning signal, the difference signal is amplified and converted to a partial value with M < N < L data bits. The partial value forms the lower-valued bits of the output value, and a bit which overlaps the reference value is used for error correction.