Showing papers on "Effective number of bits published in 1991"

Built-in self-test system and method for self test of an integrated circuit

Abstract: A built-in self-test system and method for use in testing an integrated circuit. An integrated circuit (200) includes a self-test generator (210) that produces pseudo-random test vectors, each having fewer bits than a normal input signal applied to the integrated circuit. The normal signal comprises data and parity bits that are applied to a plurality of error detection and correction (EDAC) circuits (50) on the integrated circuit. Selected bits of the pseudo-random test vectors generated by the self-test generator are fanned out to provide the total number of bits of the data and parity signals, and a test signature is produced after a full set of test vectors have been processed by the EDAC. A signature analyzer (222) compares the test signature with a predetermined expected signature to determine if a fault has occurred in one of the EDACs in the integrated circuit. The self test can be made upon demand, or alternatively, can be run pseudo-concurrently with the normal mode, using cycle stealing.

Determining ADC effective number of bits via histogram testing

Abstract: A new application for one of the widely known A/D converter (ADC) dynamic testing methods, namely the histogram method, is discussed. After computing the transition voltages of the ADC transfer characteristics, the effective number of bits is computed. Simulation shows that this method more accurately characterizes the ADC used for arbitrary input signals, compared to the fast Fourier transform (FFT) and sine-fit methods which characterize the ADC in the light of an input sinusoid. The technique outperforms sinewave fitting as it gives more accurate results, while avoiding convergence problems of the iterative curve fitting algorithm. The FFT method was verified to be the least accurate. Simulation indications that the histogram method is better than the sine-fit method are presented. >

Generalized viterbi algorithm with tail-biting

Abstract: A method and apparatus for digital radio communication employs separation of a frame of data to be transmitted into key bits, critical bits and unprotected bits. The key bits are processed to provide parity bits. The parity bits, and key bits are convolutionally encoded using a tail-biting scheme and merged with unprotected bits, and then transmitted. At the receiver, the decoder splits the received data into convolutionally encoded bits and unprotected bits, and trellis decodes the convolutionally encoded bits into a number of possible paths through a trellis using a generalized Viterbi algorithm. The tail-biting scheme reduces the number of bits that must be transmitted. Paths having errors in the key bits are rejected, and the path having the best metric without key bit errors is used in decoding the transmitted information. In the event that there is no such path, a previously selected path is substituted and decoded.

High level resolution enhancement for dual-range A/D conversion

Abstract: A dual range A/D converter includes means for appending a predetermined number N of random noise bits to the N least significant bits of the digital signals output from one of the dual A/D converters, thereby providing a total output bit resolution that is independent of the input analog signal.

Analog to digital converter

Abstract: A compact analog-to-digital converter (ADC) system suitable for high-resolution gamma-ray detectors has been developed around the Burr Brown PCM78P 16-b audio ADC. An associated application-specific integrated circuit (ASIC), handling four ADCs, provides sliding scale circuitry, lower threshold adjustment, channel number identification, and zero suppression. The conversion time is 4.5 mu s, and the differential nonlinearity, for 13-b resolution, is less than +or-0.8%. >

DRAM compressed data test mode with expected data

Abstract: A unique method of testing an integrated circuit DRAM for incorrect stored data is disclosed. A JEDEC test mode entry is initiated by normal means, i.e., Write Enable (WE*) and Column Address Select (CAS*) before Row Address Select (RAS*) with specific address data to select a specific test. Data bits are then loaded in the DRAM cells and column data bits compared. The subarray bits are also compared with bits in an expected data register which has been loaded at the beginning of the read cycle. If column bits match and subarray bits match the expected data register, ones are indicated on the data (out) bus; otherwise, a zero appears in case of a data error.

Video signal processing with added probabilistic dither

Abstract: A system in which a characteristic of individual picture points is provided to an accuracy of m binary bits but conveyed by n bits, where n is less than m. The value of a lower order bit of the n bit signal is switched to cause said binary value to represent, for any one picture point, either a value above or a value below the original value. The new values are distributed without order among the picture points with a probability dependent upon the value of the (m-n) lowest order bits of the desired value.

Coded qam system

Abstract: A block of output symbols is generated, using quadrature amplitude modulation, from a block of input bits The input bits are processed, using one or more redundant codes having a Hamming distance greater than one, to produce digital words which control the in-phase components and digital words which control the quadrature components of the output symbols A group of bits generated by a single coding step supplies bits for both types of digital word, thereby enabling that coding step to process simultaneously a larger number of bits than would be the case if separate coding were used for producing the two types of word

Current-mode cyclic ADC for low power and high speed applications

Abstract: A new current-mode cyclic ADC is proposed. An 8 bit ADC is fabricated and fully tested. The experimental results are summarised and compared with other schemes. This ADC enables a conversion time less than 10 mu s with clock frequency of 450 kHz to be obtained. The proposed ADC is found to be useful where the power and size are crucial requirements. >

General purpose system for digitizing an analog signal

Abstract: A general purpose programmable optical analyzer employs a nonlinear gain at the input stage of an analog to digital converter in order to limit the number of bits used to resolve shot noise.

Serial-to-parallel type analog-digital converting apparatus and operating method thereof

Abstract: A serial-to-parallel type A/D converter includes a resistance array, a plurality of comparators for upper bits, a plurality of comparators for lower bits, an encoder for upper bits, an encoder for lower bits and an adder. The resistance array divides a predetermined reference voltage to generate upper reference voltages, and by dividing the step width of the upper reference voltage, generates lower reference voltages. The plurality of comparators for the upper bits compare the analog input signal with the upper reference voltages, and applies the result of comparison to the encoder for the upper bits. The encoder for the upper bits calculates an estimated value of the upper bits based on the result of comparison, and select second reference voltages in the range provided by adding ±1/2 LSB to 1LSB corresponding to the estimated value of the upper bits. The plurality of comparators for the lower bits calculate the lower bits and a correcting bit based on the selected second reference voltages. The adder adds the correcting bit to the estimated value of the upper bits to correct the estimated value.

Method and apparatus for non-atomic level parity protection for storing data in a random access memory

Abstract: The method and apparatus provides a parity bit for every m multiples of b bits, a group of b bits being the smallest number of bits that can be manipulated by the CPU. The parity bit is computed for the entire m x b bits during a write operation, even if only a subset of the m multiples of b bits is being stored. The write operation is implemented as a read-modify-write operation of the entire m x b bits, with parity error reporting suppressed for the read portion of the operation. However, the parity bit is set factoring in whether a parity error is detected during the read portion of the operation. The parity bit for the entire m x b bits is checked during a read operation, even if only a subset of the m multiples of b bits is needed. Any detected parity error is reported to the CPU. As a result, hardware cost is substantially reduced with minimal degradation to data integrity. Furthermore, the method and apparatus is completely transparent to the CPU and the operating system.

Digital-to-analog converter having a circuit for compensating for variation in output dependent on temperature change

Abstract: A D/A converter converting a digital signal having n bits (n is an integer) into an analog signal includes constant-current output circuits, provided for the n bits of the digital signal, for selectively generating n constant currents on the basis of the n bits of the digital signals. The n constant currents have mutually different current values with respect to the n bits of the digital signal. The constant-current output circuits have resistance elements respectively provided for the n bits of the digital signal. The resistance elements define the mutually different current values. The D/A converter also includes an output circuit for adding the n constant currents to each other and for outputting the analog signal based on an addition result, and a temperature-dependent voltage generating part for generating a temperature-dependent voltage which changes as a temperature around the D/A converter changes. Further, the D/A converter includes a current compensation part for generating a compensation voltage related to at least one of the resistance elements from the temperature-dependent voltage and for applying the compensation voltage to the one of the resistance elements. The compensation voltage compensates for a temperature-dependent variation in a characteristic of the one of the resistance elements.

A Gray-code MOS current-mode analog-to-digital converter design

Abstract: A novel analog-to-digital converter (ADC) designed to operate without any clocking circuitry, such as a sample-and-hold, is described. The design presented is a first-generation Gray-code algorithmic converter (GA-ADC) with a continuous analog transfer function. The continuous transfer function results in a digital output that is Gray-coded. Performance degrades gracefully as the input exceeds the ADC's maximum sampling rate, enabling one to use a single ADC for a large variety of applications. In addition, the converter has other useful features such as low power dissipation, and high area efficiency. >

Full flash analog-to-digital converter

Abstract: A full flash analog-to-digital converter comprises a plurality of comparators for comparing an analog input voltage with respective reference voltages, a first-stage encoder for generating low-order bits based on output signals from the comparators, a second-stage encoder for generating high-order bits based on the low-order bits generated by the first-stage encoder, the first-stage encoder comprising a circuit for generating a complement bit of the highest-order bit of the low-order bits generated by the first-stage encoder, and the second-stage encoder comprising a circuit for generating the high-order bits based on the highest-order bit and the complement bit.

N-bit parallel input to variable-bit parallel output shift register

Abstract: N-parallel bits of data are input to a parallel in-parallel out shift register made of n+m n:1 parallel multiplexers and n-parallel bits of either pure data or combined stuff and data bits are output where, for cycles in which stuff bits are inserted, the non-outputted outputted data bits are recirculated for output on a subsequent cycle followed by newly incoming data bits; such is shown used to advantage in a bit stuffing technique where a synchronous payload envelope pattern may be started at a selected location in a synchronous transport signal frame by monitoring a frame starting signal and providing a pattern starting signal at a selected point after the occurrence of the frame starting signal.

Time shift two-step analog to digital converter

Abstract: A method of and apparatus for high speed, high resolution, time-shift two-step analog-to-digital conversion (ADC) employing only one ADC module for both coarse and fine signal conversions. The same ADC module is used first for the coarse signal conversion with its output signal stored until the ADC completes the slower fine signal conversion to generate the conversion error for the subsequent compensation process. A digital signal is then generated after the two signals are processed by using a digital signal processing to compensate for conversion error.

Improving the resolution of selected ADCs

Abstract: A technique of increasing the resolution of the counter ramp ADC (analog-to-digital converter) and successive approximation ADC without affecting their speed of operation is proposed. An n-bit simultaneous ADC is used with another m-bit successive approximation ADC or counter-type ADC to realize an (m+n)-bit ADC having the same speed of operation as an m-bit ADC. >

Dynamic random access memory device with improved power supply system for speed-up of rewriting operation on data bits read-out from memory cells

Abstract: A random access memory device includes a plurality of memory cells arranged in matrix and sense amplifier circuits for data bits read-out from a row of the memory cells, and sense amplifier circuits are provided in association with sense amplifier driving circuits selectively incorporated in a first controlling unit provided in association with row address bits for supporting propagation of the data bits. A second controlling unit is provided in association with column address bits for supporting propagation of one of the data bits to an input-and-output data buffer unit, wherein the first and second controlling units are coupled in parallel between a bonding pad supplied with a power voltage and another bonding pad supplied with a ground voltage so that the sense amplifier circuits achieve differential amplification at an improved speed.

Performance of flash ADCs in the 100 MHz range. I. Test bench and preliminary results

Abstract: Describes a systematic study of the performance of commercially available FADCs (flash analog-to-digital converter) in the 100-megasample/s range, which might be suitable for use at the Superconducting Super Collider. Performance characteristics are measured using a CAMAC-based test bench. Among the FADC performance characteristics reported are linearity, differential linearity, and the effective number of bits. >

Variable length coding method

Abstract: A variable length coding method designed to assign a different number of coding bits in accordance with the information content a sample holds when an analog signal such as a television signal or the like is converted to a digital signal. An assigning method of coding bits used to a luminance signal is different from that used to a chrominance signal. A variable length coding method is further capable of selecting an optimum assigning method in accordance with contents of an original signal from a plurality of determined assigning methods of coding bits. The data related to the plurality of assigning methods of coding bits is recorded on a medium after it is added to a coded digital signal.

A CMOS 13 bits Cyclic RSD A/D Converter

Abstract: A differential cyclic RSD A/D converter is presented where the capacitors mismatch error is corrected without extra clock-phase or added hardware. An offset error cancellation based on the RSD properties is also included. The ADC achieves 13 bits linearity at 25kS/s and dissipates 40mW. Die area is 2.25 sqmm in a 3?m CMOS process.

Improved data comparator for comparing plural-bit data at higher speed

Abstract: An improved data comparison circuit for comparing two pieces of data having 12 bits is disclosed. In the data comparison circuit, cell circuits compare two pieces of data for every corresponding 4 bits. When a match is detected in the comparison of a set of 4 bits, a signal representative of the comparison result of the lower-order bits is bypassed. That is, by bypassing a signal representative of the comparison result of the lower order bits through the cell circuit in which the match is detected, the delay of signal propagation which may occur in the cell circuit in which the match is detected can be prevented.

Charge-controlled integrating successive-approximation analog to-digital converter

Abstract: A charge-controlled integrating successive-approximation analog-to-digital converter first stores a charge proportional to an unknown voltage in a manner similar to a dual-slope integrating ADC, and thereafter a successive-approximation binary search sequence algorithm is applied to the integrator to determine digital bits representative of the unknown voltage. The result is a relatively simple and inexpensive ADC having high resolution and accuracy, and comparatively fast conversion rates, and exhibiting low power consumption, high noise rejection, and multiple-speed versatility. The preferred embodiment described is a 16-bit ADC with less than 20 millisecond conversion time.

Circuit arrangement for removing stuff bits

Abstract: The described circuit arrangement for removing stuff bits from a frame-structured signal which is available in n parallel bits, comprises a memory circuit (2) which is supplied with the parallel bits (1b). The memory circuit (2) is followed by a controllable selection circuit (3) having n outputs (3a). A control circuit (9) produces control signals (9b, 9c), which determine which bits stored in the memory circuit are transported to the n outputs (3a) of the selection circuit (3). The memory circuit (2) comprises only n delay elements by which each of the n parallel bits (1b) is delayed for the duration of one bit. So as to provide that n delay elements will be sufficient, the control circuit (9) is to block at predetermined time intervals the acceptance of new bits in one or a plurality of delay elements.

Apparatus and methods for digital-to-analog conversion using modified LSB switching

Abstract: A method and apparatus for converting a plurality of digital signals to an analog signal and m-bit digital-to-analog converter having an LSB current switch. A most significant m bits of an .[.m.]. .Iadd.n .Iaddend.bit digital signal are applied to m bits, respectively, of the m bit digital-to-analog converter, and successive values of the n bit digital signal are substituted at a first frequency. An interpolation signal is produced at the first frequency. A least significant n-m bits of the n bit digital signal are applied to the interpolation circuit to cause it to interpolate between successive values of the n bit digital signal. An LSB current switch distinct from the m bit digital-to-analog converter produces an output signal in response to the interpolation signal. An analog output signal produced by the m bit digital-to-analog converter is combined with the output signal produced by the LSB current switch to produce an analog output signal with n bit resolution. The least significant n-m bits are applied to the inputs of an n-m bit up/down counter. Causing it to count up or down from the digital value of the least significant n-m bits at a second frequency that is 2 n-m times the first frequency to thereby produce the interpolation signal on a carry output of the up/down counter. The settling times of the analog output signal occurring at the first frequency are thereby limited to the settling times of the output signal of the LSB current switch.

Analog to digital converter and comparator circuit therefor

Abstract: An ADC (18) including a comparator (40) sets, bit-by-bit, a successive approximation binary register (42). Feedback means (42, 44, 48) for auto-biasing, auto calibration, and offset compensation within the ADC (18) are provided. The ADC (18) sets itself to a high degree of accuracy automatically by reference to a master voltage reference. A number of identical ADCs (18) are connected in parallel to provide an increased sampling rate. The ADC (18) architecture compensates for component tolerance differences, for common mode noise, and for secondary parasitic effects. The ADC (18) operates with high resolution at high speed (e.g. 10 bits at 50 MHz), and can be implemented in MOS technology with good integrated circuit chip yield and is compatible with new ASICs.

Multibit oversampled DAC with dynamic matching of current sources

Abstract: Conventional binary-weighted and oversampling techniques are very popular methods of performing D/A conversions. However, the accuracy required in the component matching limits the resolution obtainable with a binary-weighted converter to approximately 8 bits, unless very sophisticated techniques (including selfcalibration) are used. Moreover, the resolution which can be achieved with an oversampled converter is limited by the oversampling factor actually obtainable for a predetermined signal bandwidth with any given integration technology. This paper presents a novel combined conversion approach, which takes advantage of the positive features of both the above techniques. The most significant bits (MSBs) are converted with the binary-weighted technique, while the least significant bits (LSBs) are converted with the oversampling technique.

5B6B coding rule inverse conversion circuit for digital transmission

Abstract: A circuit for inversely converting the signal of six bits converted by the 5B6B coding rule conversion method in the digital transmission into the original signal of five bits is described. On the occasion of inversely converting the 6-bit signal to the original 5-bit signal, the mark rate of the 6-bit signal to be converted inversely is detected in accordance with the 5B6B coding rule conversion pattern. In this case, all patterns of six bits are not detected but such six bits are divided into the upper three bits and lower three bits and the mark rates of six bits are detected from the patterns of upper three bits and lower three bits. Thereby, a number of detected patterns can be reduced and simplification of circuit structure can also be realized.

Decoder for 5B6B code

Abstract: of EP0484946A circuit for inversely converting the signal of six bits converted by the 5B6B coding rule conversion method in the digital transmission into the original signal of five bits is described. On the occasion of inversely converting the 6-bit signal to the original 5-bit signal, the mark rate of the 6-bit signal to be converted inversely is detected in accordance with the 5B6B coding rule conversion pattern. In this case, all patterns of six bits are not detected but such six bits are divided (1a, 1b) into the upper three bits and lower three bits and the mark rates of six bits are detected (2) from the patterns of upper three bits and lower three bits. Thereby, a number of detected patterns can be reduced and simplification of circuit structure can also be realized.