Showing papers on "Effective number of bits published in 1992"

Quantizer control method and apparatus

Abstract: A method and apparatus for enabling a real time video encoding system to accurately deliver the desired number of bits per frame, while coding the image only once, updates the quantization step size used to quantize coefficients which describe, for example, an image to be transmitted over a communications channel. The data is divided into sectors, each sector including a plurality of blocks. The blocks are encoded, for example, using DCT coding, to generate a sequence of coefficients for each block. The coefficients can be quantized, and depending upon the quantization step, the number of bits required to describe the data will vary significantly. At the end of the transmission of each sector of data, the method and apparatus of the invention compare the accumulated actual number of bits expended with the accumulated desired number of bits expended, for a selected number of sectors associated with the particular group of data. The system then readjusts the quantization step size to target a final desired number of data bits for a plurality of sectors, for example describing an image. Various methods are described for updating the quantization step size and determining desired bit allocations.

An 8-b 650-MHz folding ADC

Abstract: Where a flash analog-to-digital converter (ADC) needs 2/sup N/-1 comparators to convert an analog value into an N-bit binary code, an M-times folding ADC can perform this function needing slightly more than 2/sup N//M comparators. In the design reported, N=8 and the folding factor M=8. Reduction in the number of comparators is obtained by analog preprocessing of the ADC input signal. In the design considered, power consumption, chip area, and parasitic capacitance at the analog input of the ADC are reduced by using only four folding blocks and 8-times interpolation. >

Pseudo-constant bit rate video coding with quantization parameter adjustment

Abstract: A method for coding frames of video wherein a coding circuit (14,16,18) includes a processor (30) for performing an orthogonal transform such as a discrete cosine transform and a quantizer (32) for quantizing the resulting transform coefficients. The coding circuit codes the video frames using intra-frame, predictive or interpolative coding to generate code bits at a variable rate. The code bits are stored at a variable rate in a rate buffer (22), which transmits the code bits into a communication channel (24) at a pseudo-constant rate, i.e. a rate which is constant in every time interval of one frame. To maintain the contents of the rate buffer (22) within predetermined limits, the quantization parameters utilized by the quantizer (32) are periodically adjusted to increase or decrease the amount of code bits generated by the coding circuit. The quantization parameters are changed on a global SGOP level to avoid changes of quantization parameters and corresponding changes in decoded image quality within particular frames. The change in quantization parameters for coding the next SGOP is determined by a deviation measure between the actual number of code bits generated by the coding circuit (14,16,18) for the previous SGOP and an estimate of the number of code bits for the previous SGOP. The estimated number of code bits is determined based on the contents of the rate buffer (22) such that the rate buffer (22) will be emptied in a predetermined time period.

Digital encoder with dynamic quantization bit allocation

Abstract: A digital encoder for compressing a digital input signal derived from an analog signal to reduce the number of bits required to represent the analog signal with low quantizing noise. In the encoder, a digital input signal representing the analog signal is divided into three frequency ranges. The digital signal in each of the three frequency ranges is divided in time into frames, the time duration of which may be adaptively varied. The frames are orthogonally transformed into spectral coefficients, which are grouped into critical bands. The total number of bits available for quantizing the spectral coefficients is allocated among the critical bands. In a first embodiment and a second embodiment, fixed bits are allocated among the critical bands according to a selected one of a plurality of predetermined bit allocation patterns and variable bits are allocated among the critical bands according to the energy in the critical bands. In the first embodiment, the apportionment between fixed bits and variable bits is fixed. In a second embodiment, the apportionment between fixed bits and variable bits is varied according to the smoothness of the spectrum of the input signal. In a third embodiment, bits are allocated among the critical bands according to a noise shaping factor that is varied according to the smoothness of the spectrum of the input signal. All three embodiments give low quantizing noise with both broad spectrum signals and highly tonal signals.

Tap-weight controller for adaptive matched filter receiver

Abstract: In an adaptive matched filter with a decision feedback equalizer (DFE), a tap-weight controller of the matched filter includes a tapped delay line having a series of delay elements for receiving an incoming digital signal to produce successively delayed signals at successive taps of the delay line so that the signal at the center tap coincides with an output of the DFE. Cross-correlators are associated respectively with tap-weight multipliers of the matched filter. In each cross-correlator, cross-correlation is detected between a digital sample from the DFE and a delayed version of the corresponding digital sample. An average value is taken of the cross-correlation to produce higher significant bits of a tap-weight coefficient for the corresponding tap-weight multiplier. The most significant bit of the output of the higher significant bits is inverted and a group of bits is produced, each having the same binary value as the inverted most significant bit. The group of bits is supplied to the corresponding tap-weight multiplier as lower significant bits of the tap-weight coefficient.

Error correction system for n bits using error correcting code designed for fewer than n bits

Abstract: A computer system includes an error detection and correction system for detecting and correcting single-bit errors, two-adjacent-bit errors, and four-adjacent-bit errors. Two identical error detection and correction (EDC) circuits are connected to the system memory array, and each EDC circuit is connected to half of the data bits in alternating pairs. Each EDC circuit detects single-bit errors and two-adjacent-bit errors. The EDC circuits are connected to alternating pairs of data bits so that errors of up to four adjacent bits are actually detected and corrected, two bits by the first EDC circuit and two bits by the second. Thus, if one of the x4 DRAMs in a memory array fails, each erroneous data bit from the DRAM is corrected to its original value, and the failure of the DRAM is registered.

Low bit rate vocoder means and method

Abstract: Efficient coding speech information for low rate (e.g., 600 bps) channels using a four frame superframe (SF) includes: (1) coding spectral information using alternative quantizers one of which is chosen for each superframe so that 3 bits/SF identify the optimal quantizer and 28-32 bits/SF contain the quantized spectral information; (2) coding pitch using 5 bits/SF if voiced and if unvoiced assigning the pitch bits to error correction; (3) coding energy using 9-12 bits/SF by a 4d vector quantizer (4dvQ); and (4) coding voicing using 3-4 bits/SF by a 4d VQ, for a total of 54 bits/SF including 1 sync bit and 0-1 error correction bits. When combined with a unique perceptual weighting scheme, output speech quality comparable to that of vocoders operating at almost four times the channel capacity is obtained.

Successive approximation analog to digital converter employing plural feedback digital to analog converters

Abstract: There is disclosed an ADC including a comparator which sets, bit-by-bit, a successive approximation binary register. Feedback means for auto-biasing, auto-calibration, and offset compensation within the ADC are provided. The ADC sets itself to a high degree of accuracy automatically by reference to a master voltage reference. A number of identical ADCs are connected in parallel to provide an increased sampling rate. The ADC architecture compensates for component tolerance differences, for common mode noise, and for secondary parasitic effects. The ADC operates with high resolution at high speed (e.g., 10 bits at 50 MHz), and can be implemented in MOS technology with good circuit yield and is compatible with ASICs.

Monotonic current/resistor digital-to-analog converter and method of operation

Abstract: A digital-to-analog converter (10) performs two distinct conversions (12,59) of most significant bits (MSBs) and least significant bits (LSBs), respectively, of a digital input signal and uses the conversion results to provide an equivalent analog output. A plurality of current sources (34-36) is controlled by a thermometer code equivalent value of the most significant bits to provide a first input current to an output stage (22). A plurality of resistors (60-63) is controlled by a binary to `one of` equivalent of the least significant bits to provide a second input current to the output stage. The output stage (22) converts a combination of the first and second input currents to the analog output.

Synchronization scheme for a digital communications system

Abstract: A synchronization scheme for a digital communications system wherein customer data is connected to a synchronous communications network utilizes auxiliary symbols (403-406) to provide frame synchronization. Each such auxiliary symbol lies outside of a conventional symbol constellation and is only used to represent framing information. Variations of the customer data rate relative to an expected rate are compensated for by the use of stuff and delete bits in each frame. These bits can be either customer data bits or ancillary bits depending on the direction of this variation. Advantageously, the auxiliary symbols also provide a determination of whether the stuff and delete bits in any frame are customer data or ancillary bits.

Multi-bit sigma-delta analog-to-digital converter with reduced sensitivity to DAC nonlinearities

Abstract: A multi-bit sigma-delta analog-to-digital converter (ADC) (40) includes a sigma-delta modulator (41) with a multi-bit quantizer (46) and a digital-to-analog converter (DAC) (47) An output of the DAC (47) provides an error signal of the modulator (41) The quantizer (46) provides a quantized signal having multiple bits ordered from a most-significant bit, to a second most significant bit, to at least one lower-order bit including a least-significant bit At least two of these bits, including the most significant bit and one of the lower-order bit or bits, are provided as inputs to the DAC (47) The remaining bits are provided as inputs to a prefilter (49), which performs the same transfer function as a comparable multi-bit modulator A summing device (49) subtracts the output of the prefilter (48) from the quantized signal A decimation filter (50) resamples the output of the summing device (49) to provide the output of the ADC (40)

Current/resistor digital-to-analog converter having enhanced integral linearity and method of operation

Abstract: A digital-to-analog converter (10) uses series-connected resistors (55-59) to implement conversion of most significant bits of a digital input signal to an equivalent analog output signal. Current sources (22-26) are used to implement conversion of least significant bits of the digital input signal to the analog output signal. After making a binary-to-thermometer code conversion of the least significant bits, first logic circuitry (70) provides control signals (SI) for controlling the switching of each of the current sources to either a first (42) or a second (44) node. After making a binary to `one of` code conversion of the most significant bits, second logic circuitry (86) provides control signals (SR) for respectively switching the first and second nodes to any two resistor nodes of the resistors. The resistors are connected between a reference voltage terminal and a third node where the analog output signal is developed.

Progressive bit plane reconstruction method

Abstract: An method and associated apparatus for mapping received bits in a progressive bit plane scheme to output values which are derived by combining all previously received bits with the most recently received bits and appending additional bits to provide output values that are distributed across the output display range so as to improve recognizability of reconstructed images when only a few bit planes have been received.

Error protection for multimode speech coders

Abstract: A method for protecting information bits wherein input data bits, at least some of which are to be protected, are sorted based upon information determined from a subset of the input data bits. An error control coding technique is applied to at least some of the sorted bits. In the preferred embodiment, an input data stream of voice coder bits is separated into arrays of bits. A first array (302) comprises voice coder bits needing error protection, with the bits arranged in order of importance determined by voicing mode. The second array (303) comprises bits that will not be error protected. The bits from the first array are provided to the input of an encoder (304), then the encoded bits are combined (305) with the bits from the second array (303) to form a bit stream.

A 10 b 50 MS/s pipelined ADC

Abstract: Most multistep analog-to-digital converter (ADC) architectures presented thus far suffer from poor linearity caused by the sample and hold as well as the internal digital-to-analog converter (DAC). Furthermore, the gain-matching between coarse and fine ADC gives rise to nonmonotonicity. A fully differential two-step ADC is described which presents solutions for sample and hold, the DAC, the gain-matching between coarse and fine high performance with low power consumption and small chip area. >

Variable bit rate adaptive predictive coder

Abstract: An adaptive predictive coder providing almost toll quality at 16 kb/s and minimal degradation when the bit rate is lowered to 9.6 kb/s is described. The coder can operate at intermediate bit rates and can also change bit rate on a packet-by-packet basis. Variable bit rate operation is achieved through the use of switched quantization, thus eliminating the need for buffering of the output. A noise shaping filter provides flexible control of the output noise spectrum. The filter, in conjunction with an enhanced way to adapt the quantizer step size, which tries to accommodate the quantization noise feedback, accounts for the toll quality. By quantizing the residue with more than one quantizer, the effective number of bits per sample can be controlled in a deterministic way regardless of the entropy residue. The lower limit of operation is at 9.6 kb/s. Performance of the coder under random bit errors is also presented. It has been found that only at error rates of 10/sup -2/ and higher does the degradation becomes objectionable. >

Method of compressing digital image data and device thereof

Abstract: A method of compressing digital image data and a device thereof of coding digital image data within constant rate data not deteriorating a resolution of an image without regard to a complexity of digital image data. A format of M×N pixel blocks (where M, N are natural numbers) is made from luminance and sub-sampled chrominance signals, and first to fourth edge values TY, TR-Y, TB-Y, Ai respectively from the luminance, sub-sampled signals and the blocks are detected. A quantization scaling factor is determined by normalizing the first edge value, and the number of bits corresponding to the each block is allocated according to the first to fourth edge values. The number of AC (alternating current) factor bits is allocated by subtracting the number of DC (direct current) factor bits of the each block coded by a one-dimensional Huffman coding from the number of the allocation bits.

Investigations and measurements of the dynamic performance of high-speed ADCs

Abstract: Investigations concerning the origin of the aperture jitter in a 4-b parallel analog-to-digital converter (ADC) implemented in a 0.5- mu m GaAs FET technology have been undertaken. On-chip electron-beam measurements of the comparator clock distribution show a deviation of 20 ps between the comparators. Simulation considering process variations shows similar results. To overcome these problems, a GaAs 5-b, 1-Gsamples ADC with on-chip track-and-hold circuitry (T&H) has been developed. A complete DC and AC characterization of the ADC using a histogram test, fast Fourier transform test, sine wave curve-fitting test and beat frequency test up to 1.3 GHz was performed. The measurement set-up consisted of a 4-GHz sine wave generator, a 10-GHz pulse generator, an 8-b wide 700-MHz digital acquisition system for data recording, and a PC. By using the T&H in front of the parallel ADC, 4.6 effective number of bits (ENOB) has been achieved at 1-GHz input signal compared to 3.7 ENOB without T&H. A comparison of the different test methods and results is given. >

Histogram-based distortion and gain tracking testing of an 8-bit PCM mixed analog-digital IC chip

Abstract: The effective number of bits of a linear analog-to-digital converter (ADC) can be computed using the code density histogram method. The technique is adapted to test an oversampling or sigma-delta ( Sigma Delta ) converter. It is assumed that the device under test includes a Sigma Delta modulator, a decimator, and a mu -law compressor. The analog stimulus to the device under test is supplied by a precision signal generator, and the code density histogram of the 8-b mu -law compressed output of the ADC is analyzed to determine whether the converter is performing within its specifications. Simulation results which were obtained using a very simple model for the ADC and additive white Gaussian noise are presented. >

Analog to digital converter system

Abstract: An A/D converter system has an A/D converter element (10) which provides a first predetermined number of digital output bits for each input analog signal. An addition device (12,70) adds linear slope potential to the input analog signal. A calculator (14) provides an average of a plurality of digital output signals of the A/D converter element so that the average has larger number of bits than the first predetermined number. The addition device is implemented by a time constant circuit (70) which functions as an integral circuit for an input analog signal, and functions as a differential circuit for a slope potential.

Enabling data access of a unit of arbitrary number of bits of data in a semiconductor memory

Abstract: A DRAM device includes a read control circuit for inhibiting read out of one or more bits of a multi-bit data output from a plurality of memory cells in response to a bit designating signal for specifying the one or more bits. By arbitrarily setting the number of bits to be output from the DRAM device and combining that output with data from one or more additional memory devices, data of an arbitrary number of bits can be generated at a high speed.

Error detecting and correcting apparatus and method with transparent test mode

Abstract: System for testing memory associated with a set of check bits in an EDC system. The circuitry of the invention includes an EDC circuit; multiplexers; and a memory with first storage bits, second storage bits, and third storage bits. In writing data to the memory, a multi-bit data word having a first group of data bits and a second group of data bits is first received from a CPU bus. The first group of bits is written to the first storage bits. In a "normal" mode, the second group of bits is written to the second storage bits. A set of check bits are calculated by the EDC circuit and written to the third storage bits. In the "swap" mode, the second group of data bits is stored in the third storage bits. "Alternate" bits are calculated by the EDC circuit, and written to the second storage bits. In memory reads, contents of all of the storage bits are received from the memory and directed to the error detecting circuit. The contents of the first storage bits are directed to error correction circuit. In the normal mode, the contents of the second storage bits are directed to the error correction circuit; this data is corrected if necessary, and placed on the CPU bus. In the swap mode, the contents of the third storage bits are supplied to the error correcting circuit and, along with the contents of the first storage bits, placed on the CPU bus without error correction.

Address translator having a high speed data comparator

Abstract: An address translator has an improved data comparison circuit for comparing two pieces of data having n bits, e.g., 12 bits. In the data comparison circuit, cell circuits compare two pieces of data for every corresponding 4 bits. When a match is detected in the comparison of a set of 4 bits, a signal representative of the comparison result of the lower-order bits is bypassed. Hence, delay of signal propagation which may occur in the cell circuit in which the match is detected is reduced.

Analog to digital converter with increased resolution

Abstract: An A/D converter system has an A/D converter element (10) which provides a first predetermined number of digital output bits for each input analog signal, an addition means (12,70) for adding linear slope potential to said input analog signal, and a calculator (14) for providing an average of a plurality of digital output signals of said A/D converter element so that said average has larger number of bits than said first predetermined number. Said addition means is implemented by a time constant circuit (70) which functions as an integral circuit for an input analog signal, and functions as a differential circuit for a slope potential.

Incidence of the resolution and the differential nonlinearity of a A/D converter on high dynamic signal measurement experimental characterization

Abstract: Accurate measurement of highly dynamic signals is considered. A method for characterizing analog-to-digital converter (ADC) input noise and threshold is presented. Its application allows the theoretical effect of ADC nonlinearity and resolution errors to be identified. Two methods of improving ADC resolution and differential nonlinearity correction are proposed. With these methods, an 8-b ADC can measure highly dynamic signals with an accuracy as great as that of a 10-b ADC and the sampling rate limit is improved. The correction methods enable the resolution limit to be increased for repetitive high-frequency signals. The efficiency of these methods is only limited by the apparatus drift. >

Improved dynamic compensation of ADCs using an iterative estimate of the ADC calibration signal

Abstract: An iterative improvement of current analog to digital converter (ADC) dynamic compensation schemes is introduced. The improved calibration procedure uses an improved estimate of the ADC input during calibration. Simulation results which implement the algorithm demonstrate an improvement in the spurious free dynamic range for a compensated 8-b converter of 30 to 40 dB over the performance of the uncompensated converter. >

Noise shaper circuit

Abstract: According to this invention, a noise shaper circuit capable of realizing an integrated circuit having a small chip area is provided. In calculating circuits for calculating input data represented by a twos complement and feedback data of output data converted into data having a small word length, the input data is divided into upper bits and lower bits with respect to a bit rounded off during a word length converting operation, only the upper bits are used in a calculation, and the calculation result and the lower bits which are not used in the calculation are added to the LSB of the calculation result again, and the resultant data is output to the next stage.

A low power 12-bit ADC for nuclear instrumentation

Abstract: A low-power, successive-approximation, analog-to-digital converter (ADC) for low-rate, low-cost, battery-powered applications is described. The ADC is based on a commercial 50-mW successive-approximation CMOS device (CS5102). An on-chip self-calibration circuit reduces the inherent differential nonlinearity to 7%. A further reduction of the differential nonlinearity to 0.5% is attained with a four-bit Gatti function. The Gatti function is distributed to minimize battery power consumption. All analog functions reside with the ADC, while the noisy digital functions reside in the personal-computer-based histogramming memory. Fiber-optic cables carry all digital information between the ADC and this memory. >

A 12 b 20 MS/s ripple-through ADC

Abstract: The characteristics of a 12 b 20 MS/s ripple through analog-to-digital converter (ADC) are described. The one-bit-per-stage ripple-through architecture used in this 12-b ADC requires only 21 comparators and one track and hold for 12-b resolution, resulting in a smaller die (18 mm/sup 2/) and 7 to 14 dB better signal to noise and distortion ratio (SNDR) than previous 10-b converters. >

An 8-bit 22-MHz recycling two-step ASIC ADC with integrating sample and hold

Abstract: A recycling two-step architecture with a very low input current comparator is presented to implement an 8-b analog-to-digital converter (ADC) with an integrating sample and hold circuit that yields a 22-Msps conversion rate with a 10-MHz input. This two-step recycling architecture makes use of a novel switch circuit design reducing the number of components required for the complete ADC. The ADC is realized using 900 transistors on two-metal, f/sub T/=8.5 GHz, npn bipolar junction transistor (BJT) application-specific integrated circuits. >