Showing papers on "Effective number of bits published in 1996"

Apparatus and method for selecting a coding mode in a block-based coding system

Abstract: An apparatus and concomitant method for selecting a macroblock coding mode based upon the quantization scale selected for the macroblock. The total number of bits needed to code each macroblock consists of two parts, bits needed for coding motion vectors (320) and bits for coding the predictive residual (330). The number of bits for coding the motion vectors is generally obtained from a look-up table. The number of bits for coding the predictive residual is obtained by an estimation which assumes that the number of bits for encoding the predictive residuals is directly proportional to the value of its variance and inversely proportional to the value of quantizer steps (quantizer scale). Using this estimation, the total number of bits necessary to code a macroblock is calculated (340) and compared for each coding mode (350). By selecting the coding mode with the least number of bits, a near-optimal solution of low complexity for practical implementation is acquired.

Transmitter for encoded data bits

Abstract: Quadrature Amplitude Modulated signals are generated from data bits by using a first Quadrature Phase Shift Keying (QPSK) modulator for encoding a first pair of the data bits into one of four carrier signal phases, thereby producing a first QPSK signal. A second QPSK modulator encodes a second pair of the data bits into one of four carrier signal phases, thereby producing a second QPSK signal. The first QPSK signal is amplified to a first power level, and the second QPSK signal is amplified to a second power level. The first and second amplified signals are then combined to produce a signal in which four data bits are encoded. In another aspect of the invention, a new type of modulation, called Offset Quadrature Phase Shift Keying (OQPSK), is used in place of the first and second QPSK modulators, so that an Offset Quadrature Amplitude Modulation (OQAM) transmitter is formed. An OQPSK modulator encodes data bits by encoding a first sub-group of the data bits into a real part of a complex signal at an odd instant of a clock, and by encoding a second sub-group of the data bits into an imaginary part of the complex signal at an even instant of the clock. OQPSK modulation provides the benefit of having all signal transitions being constrained to trajectories around constant radius circles, thereby producing spectral efficiency.

Error detection and correction

Abstract: A computer system includes a processor bus having processor data and processor check bits for performing error detection and correction of the processor data. A CPU is coupled to the processor bus. A memory sub-system is coupled to the processor bus and includes memory check bits, memory address bits, and memory data bits, and an error detection and correction device for detecting an error in the memory address bits using the memory check bits and for detecting an error in the memory data bits using the memory check bits. The CPU can include a processor from the Pentium® Pro family of processors. The error detection and correction device generates a syndrome table which includes a plurality of entries mapped to correctable or uncorrectable errors, in which a detected multiple-bit error in the memory data bits is mapped to an uncorrectable error entry and a detected error in the memory address bits is mapped to an uncorrectable error entry. An error detection device is also coupled to the processor bus for detecting an error in the address bits or data bits using the processor check bits.

System and method for encoding data to reduce power and time required to write the encoded data to a flash memory

Abstract: A method and system in which X-bit packets of bits (where X is an integer) are encoded to generate X-bit packets of encoded bits for writing to erased cells of a flash memory array, where less power is consumed to write a bit having a first value to an erased cell than to write a bit having a second value to the cell. Preferably, a count signal is generated for each packet of raw bits indicating the number of bits of the packet having the first (or second) value, the count signal is processed to generate a control signal which determines an encoding for the packet, and the raw bits of the packet are encoded according to a scheme determined by the control signal. In some embodiments, each erased cell is indicative of the binary value "1", the count signal is compared to a reference value (indicative of X/2) to generate a control signal determining whether the packet should undergo polarity inversion, and the packet is inverted (or not inverted) depending on the value of the control signal. In alternative embodiments, a count signal is generated for each packet of bits to be written to erased cells of an array (where the count signal indicates the number of bits in the packet having a particular value), and each packet is encoded in a manner determined by the corresponding count signal to reduce the power needed to write the encoded bits to the erased cells. Preferably, flag bits indicative of the encoding of each packet are generated, and the flag bits (as well as the encoded packets) are stored in cells of the flash memory array.

Error checking and correcting for burst DRAM devices

Abstract: A method is described of detecting and correcting errors in a computer having a memory subsystem including a burst DRAM device. The method includes the steps of beginning a write operation of N data bits to the burst DRAM device, generating M check bits from the N data bits, writing the N data bits and the M check bits to the burst DRAM device, reading the N data bits and M check bits from the burst DRAM device, generating X syndrome bits from the N data bits and the M check bits, and using the X syndrome bits to detect and correct any single bit error within the N data bits and the M check bits and to detect any double bit error within the N data bits and the M check bits. A computer system is also described having a central processing unit and a memory subsystem. The memory subsystem includes a burst DRAM device, a memory controller arranged to control the burst DRAM device in response to instructions received from the central processing unit, data format conversion circuitry arranged to convert between a data format readable by the burst DRAM device and a data format readable by the memory controller, and ECC circuitry arranged to encode a data word with an error correction code in response to a write instruction and to decode the data word and conduct error correcting and detecting in response to a read instruction.

Intermediate frequency (IF) sampling clock-to-clock auto-ranging analog-to-digital converter (ADC) and method

Abstract: A clock-to-clock auto-ranging ADC operates directly on an analog signal in the IF band or higher to track its gain range on a clock-to-clock basis and produce a digital signal that maintains high resolution of the analog signal without clipping or loss of signal sensitivity. This is accomplished by sampling an analog signal of sufficiently high frequency that a peak detector can accurately determine the maximum signal level over at least one-half a signal period and then reset the signal gain going into the ADC prior to the beginning of the next sampling period. This insures that the analog signal will always be within the range of the ADC. In accordance with the well known principles of sampling theory, the sampled analog signal is aliased into the frequency region between DC and one half the sampling frequency.

A full Nyquist 15 MS/s 8-b differential switched-current A/D converter

Abstract: This paper describes the architecture and circuit design of an experimental 8-b differential 15 MS/s CMOS A/D converter, implemented using the switched-current (SI) technique. Particular emphasis has been given to maintaining analog bandwidth and hence the effective number of bits right across the input Nyquist band. Individual cells have also been optimized for inherent accuracy to achieve good performance in a simple uncorrected conversion algorithm. The converter is fabricated in a standard 0.8 /spl mu/m 5 V digital CMOS process and occupies 2.4 mm/sup 2/.

Output data compression scheme for use in testing IC memories

Abstract: A memory system operable in a normal mode of operation and a test mode of operation includes sensing circuitry which generates x number of data bits during a read cycle. A read path circuit, coupled to the sensing circuitry, transfers the x number of data bits generated by the sensing circuitry during a first read cycle in the normal mode of operation to x number of output nodes. A first detection circuit, coupled to the read path circuit, detects whether or not the x number of data bits generated by the sensing circuitry during a second read cycle in the test mode of operation are arranged in a pattern in which all bits are identical. A second detection circuit, coupled to the read path circuit, detects whether or not the x number of data bits generated by the sensing circuitry during the second read cycle in the test mode of operation are arranged in a pattern in which each two adjacent bits are different. An output circuit, coupled to the first and second detection circuits, generates y number of output data bits which are arranged in a pattern indicative of whether the x number of data bits generated by the sensing circuitry during the second read cycle in the test mode of operation are identical, are arranged in a pattern in which each two adjacent bits are different, or are arranged in another pattern, and wherein y is less than x. A method of testing an integrated circuit (IC) memory is also disclosed.

Accuracy of effective bits estimation methods

Abstract: The basic assumptions of analog-to-digital converter (ADC) effective bit estimation procedures are analyzed and closed-form expressions that link accuracy to the parameters that describe the measurement conditions are derived. It is shown that the achievable accuracy mainly depends on the ratio between the number of acquired samples and the number of ADC quantization levels. Furthermore, the effect of broad-band noise superimposed to the sinewave employed as test input is analyzed. Results useful for the design of the estimation procedure itself are also provided.

Method and apparatus for utilizing a data processing system for multi-level data communications providing self-clocking

Abstract: A method and apparatus utilizing a data processing system are disclosed for multi-level data communication providing self-clocking. A first digital signal is input which includes a series of digital bits. One of a plurality of output levels is associated with each group of data bits for each of the plurality of the digital bits included within the first digital signal. A particular output level is associated with a clock output level. An output signal is generate which includes a transmission of the output level for each of the groups of digital bits and includes multiple transmissions of the clock output level, where a clock output level is transmitted after each transmission of an output level for each of the groups of digital bits.

Two stage analoge-to-digital converter having unique fine encoding circuitry

Abstract: An analog to digital converter for the conversion of an analog input signal to a digital output code of n bits has a plurality of voltage references created in a voltage reference generator that divides the total range of voltage of the conversion input into increments of voltage equal to the smallest increment of resolution. The n bits of digital output are divided into most significant bits and least significant bits. The most significant bits are encoded from a set of digital signals that are formed in a set of coarse comparators, that compare the analog input signal with a subset of the voltage references representing the coarse range. The digital code that is the output of the coarse comparators is used to determine the selection of the subset of the plurality of the voltage references that are the fine voltage references. The least significant bits are encoded from a set of digital signals that are formed in a set of fine comparators that compare the analog input signal to the fine voltage references. The digital codes that form the most significant bits and the least significant bits are corrected encoded in an output encoder to form the digital output word.

Methods and structure for sampled-data timing recovery with reduced complexity and latency

Abstract: Analog-to-digital converter (ADC) output bits are partitioned in a way that simplifies the phase error calculations. The circuit architecture embeds the implementation of the phase error calculations in the analog-to digital-converter (ADC) to simplify the overall circuit implementation. Simplification of the phase error calculations allows a reduction in the complexity of the circuits needed to implement the phase-locked-loop (PLL) for recovering the sampling clock.

Digital signal processing device and display using the same

Abstract: PROBLEM TO BE SOLVED: To realize a high quality signal processing circuit by removing operational error accumulation when signal processing is performed with a limited number of bits and removing tone skip when a digital video signal is gamma- controlled. SOLUTION: For example, the lower 2 bits su0 and su1 of the digital video signal are generated from the lower 2 bits si0 and si1 including the least significant bit si0 of the 8-bit input digital video signal SU by a lower bit generating circuit 1. Then, by delaying the input digital video signal SI by a delay circuit 2 and synchronizing the timing to the bits su0 and su1, the bits si0 to si7 of the input digital video signal SI are set as the upper 8 bits su2 to su9 of the digital video signal SU. Thus, for example, gamma control processing is performed to the digital video signal SU expanded into 10 bits by the signal processing circuit, and outputting a digital video signal SV after processing as an 8-bit signal. COPYRIGHT: (C)1998,JPO

Addition overflow detection circuit

Abstract: The invention provides an addition overflow detection circuit which can detect an addition overflow at a high rate even where the output bit number is remarkably smaller than the input bit number and which is realized with a comparatively small amount of hardware. An unsigned augend and an unsigned addend of the n bit length are individually divided into lower m bits and upper n-m bits. The lower bits are inputted to an adder, and a carry from the (m-1)th bit to the mth bit is detected from the output of the adder. The upper bits are inputted to both of two fast adder-comparators, by which it is detected that all bits of the sum of them are equal to 1 or 0, respectively. In response to presence or absence of the carry, one of detection outputs of the fast adder-comparators is selected and logically inverted to obtain an overflow detection result.

Two error-detecting and correcting circuits for space applications

Abstract: The paper describes two error detection and correction (EDAC) circuits designed and manufactured for the European space program. One of the EDACs is for a 16 bit data bus and the other for a 32 bit data bus. Eight check bits are added to the 16/32 data bits, giving the possibility to correct all single errors (SEC), detect all double errors (DED) and detect any memory chip failure (SBD), with a 4 or 8 bit per chip organization. Generally, SEC-DED-SBD require more check bits than the number of bits per chip. However, assuming all chip errors (but not the bit errors) to be permanent, the implemented (40,32) and (24,16) codes can be used to obtain SEC-DED-SBD for a 8 bit per chip organization. For a memory having 4 bits per chip, the codes are true SEC-DED-SBD. The codes are constructed by. Adding extra check bits to a reorganization of ordinary odd weight column SEC-DED codes. The extra check bits are considered not to require any extra memory, since the number of memory chips needed are the same for 22 as for 24 (39 as for 40) bits, when the organization is by 4 or by 8.

Non-volatile multi-state memory device capable with variable storing resolution

Abstract: This non-volatile multi-state memory device switches a storing resolution of multi-state data corresponding to digital data stored in a non-volatile memory cell according to the data's characteristics. In more detail, digital audio data are output from an ADPCM encoder (2) in n-bit units and m bits of address data indicating an address at which audio data are stored are output from an address controller (9). These are then input to a switching circuit (12), a bit number converting circuit (13) converts m bits of address data to n bits of address data at the same level as the m bit data, and the converted n bits of address data and n bits of audio data are inputted to a second multiplexer (15). An output of the Second multiplexer (15) is then selected in compliance with a switch signal from the address controller (9) and either the selected n bits of address data or the audio data are sent to a read-write circuit (42). Consequently, for example, writing is carried out with storing resolution deemed as 16 when 4 bits of audio data are stored in an EEPROM cell array (3) and storing resolution deemed as 2 when for instance 1 bit of address data is stored.

Address comparing for non-precharged redundancy address matching with redundancy disable mode

Abstract: An integrated circuit includes primary circuit elements selectable by n address bits. A master storage device is programmable to indicate that at least one primary circuit element is being replaced. Redundant circuit elements each include a non-precharging matching circuit, which includes sub-match circuits. The sub-match circuits include two state storage devices corresponding to one of the possible binary values of at least one of the n address bits and activate a sub-match signal when the binary value of the at least one of the n address bits corresponds to one of the two state storage devices in a first state if the master storage device is programmed. A match circuit activates a match signal in response to all sub-match signals being active to disable a primary circuit element from being selected by a corresponding binary value of the n address bits and to enable the redundant circuit element to be selected by the corresponding binary value of the n address bits. In one form of the integrated circuit, each sub-match circuit includes redundancy disable circuitry responsive to a redundancy control signal being in a first state to deactivate an activated sub-match signal.

System and method for encoding data such that after precoding the data has a pre-selected parity structure

Abstract: A system comprises an encoder, a precoder, a PR channel, a detector, and a decoder. An input signal is received by the encoder. The encoder generates a code string by adding one or more bits and outputs the code string to the precoder. The encoder applies such encoding such that the code string after being modified by the precoder has a pre-selected parity structure. The encoder provides a systematic encoding scheme in which many of the encoded bits are the same as the input bits used to generate the encoded bits. This systematic approach of the present invention provides an encoder that is easy to implement because a majority of the bits are directly "feed through" and non-trivial logic circuits are only needed to generate the control bits. The systematic encoding also dictates a decoder that is likewise easy to construct and can be implemented in a circuit that simply discards the control bit. The encoder preferably comprises a serial-to-parallel converter, a code generator and a parallel-to-serial converter. The code generator produces one of three trellis codes such as a rate 8/9, 8/10 or 9/11 code. The present invention also includes a method that is directed to encoding bit strings and comprises the steps of: 1) converting the input string to input bits, and 2) adding at least one bit to produce a pre-selected parity structure after precoding.

Current source referenced high speed analog to digitial converter

Abstract: An architecture for a high speed analog current to digital voltage converter particularly suited for integrated circuit applications. As preferably implemented, an analog signal of current form and an associated reference current are generated on a source integrated chip. The reference current line and one or more analog current lines transmit data between the source and a receiving integrated circuit chips. The high speed converter utilizes current mirrors to simultaneously evaluate the analog inputs and determine the digital equivalents through current comparisons using currents derived from the reference current. The architecture provides for switching of current sources in lower order bits responsive to the detection of input currents enabling higher order bits. Since switching of lower order bits by higher order bits is accomplished simultaneously, the analog current to digital voltage conversion is accomplished within one switch period while retaining the relatively high accuracy.

Tri-step analog-to-digital converter

Abstract: An analog to digital converter for the conversion of an analog input signal to a digital output code is disclosed. The analog to digital converter has a voltage reference generator to create a plurality of voltage references that divides the total conversion range of the input into increments equal to the smallest resolution increment. The digital output code is divided into most significant bits, intermediate significant bits and least significant bits. The most significant bits are encoded from a set of coarse digital signals that are formed in a set of coarse comparators. The coarse digital code is used to determine the selection of the sub-coarse voltage references. The intermediate significant bits are encoded from a set of subcoarse digital signals. The subcoarse digital code that and the coarse digital code are used to determine the selection of the fine voltage references. The least significant bits and a correction factor for the intermediate significant bits are encoded from a set of fine digital signals. The digital codes that form the most significant bits, the intermediate bits, the fine bits, and the correction factor are encoded in an output encoder to form the digital output word.

Multiplexed text data sampling circuit

Abstract: A multiplexed text data sampling circuit comprises a detecting signal inhibiting circuit (3) for inhibiting delivery of a detecting signal indicating a detection of a start bit of text broadcasting data from a start bit detecting circuit (2) during a predetermined period of time before the start bit appears, and a variable divider (71), responsive to the detecting signal, for dividing a clock signal so as to produce a sampling clock signal to sample the text broadcasting data, and for varying a dividing ratio between the frequency of the clock signal and the frequency of the sampling clock signal in such a manner that the sampling timing for each of bits of the text broadcasting except one or more last bits is adjusted so that each bit except the one or more last bits is sampled in the middle of a period of time during which each bit except the one or more last bits is applied to the sampling circuit, and the sampling timing for each of the one or more last bits is adjusted so that each bit of the one or more last bits is sampled at an earlier time of a period of time during which each bit of the one or more last bits is applied to the sampling circuit.

Hadamard transform coding/decoding method and apparatus for image signals

Abstract: In a Hadamard transform coding/decoding method and apparatus, transform coefficients which are obtained through an Hadamard transform operation in an Hadamard transformer 3 are subjected to a bit extract (delete) operation in a bit delete unit 4 to extract 1 bit from the least significant bits of the transform coefficients, 4 bits from the second least significant bits and 7 bits from the third least significant bits and then the extracted bits are output as supplement information Ysup. In addition, the transform coefficients whose first, second and third least significant bits are deleted, are output from the bit delete unit 4. A bit restoring unit 7 supplements the first, second and third least significant bits of all the transform coefficients on the basis of the 1-bit information, 4-bit information and 7-bit information per block of the supplement information Ysup, which represent the first, second and third least significant bits of the transform coefficients, thereby restoring the transform coefficients. The restored transform coefficients are output to an Hadamard inverse transformer 8 to obtain an image signal.

Digital-to-analog converter test method and apparatus

Abstract: A method and apparatus for testing the linearity of a digital-to-analog converter that uses equally-weighted signal sources to convert high-order bits of digital input, and unequally-weighted signal sources to convert low-order bits. Minimum and maximum digital inputs are supplied, and a linear input-output characteristic is calculated from the two resulting analog output values. The nonlinearity error is calculated by finding the deviations from this linear input-output characteristic of two sets of analog output values: one set obtained by varying the high-order bits while holding the low-order bits constant; the other set obtained by varying the low-order bits while holding the high-order bits constant.

Digital-to-analog converter circuit using current mirror circuit for conversion of law-order bits

Abstract: A digital-to-analog converter circuit is configured by a digital-to-analog converter receiving data of m bits (where `m` is an integer arbitrarily selected), a voltage-follower circuit containing an operational amplifier, a current-mirror circuit and a current-switching circuit. Herein, the data of m bits are extended by bits b H and b L in low-order positions thereof, wherein b H is placed in a higher order than b L . A noninverting input of the operational amplifier is connected to an output of the digital-to-analog converter; and a feedback resistor is connected between an inverting input and an output of the operational amplifier. The current-mirror circuit, using MOS transistors, provides two constant currents I H and I L in response to the bits b H and b L respectively, wherein a relationship between the constant currents I H and I L is defined by an equation of I H =2×I L . The current-switching circuit, which is connected between the current-mirror circuit and the voltage-follower circuit, is designed to selectively switch the two constant currents to be supplied to the inverting input of the operational amplifier in accordance with values of the bits b H and b L . Thanks to the configuration of the digital-to-analog converter circuit, the feedback resistor and the current-mirror circuit can be designed for small areas. Hence, it is possible to easily extend a number of bits without greatly enlarging the size of the digital-to-analog circuit.

A low power 10-bit 300 kS/s RSD coded pipeline A/D-converter

Abstract: This paper describes a 10-bit 300 kS/s analog-to-digital converter fabricated in a 0.8-/spl mu/m CMOS technology. The main objective was to minimise the power consumption of the circuit. This was achieved by using an interleaved pipeline structure with only one operational amplifier per stage. The current consumption of the converter circuit is 2 mA from 2.7 V power supply when using a power saving scheme in which the resolution per stage is moderately relaxed towards the LSB. The digital RSD (Redundant Signed Digit) principle is used to correct the errors caused by the mismatch in the gain factor 2 and the comparator offsets. The measured SNR was 58.5 dB, ENOB 9.4 bits, typical INL +/-1.5 LSB and DNL +/-0.5 LSB. The active chip area is 1.3 mm/sup 2/, excluding pads.

High-speed read-out semiconductor memory

Abstract: In order to decrease peak value of current consumed by sense amplifiers provided in a high-speed read-out semiconductor memory for sensing and amplifying data of certain words of addresses having the same upper bits with upper bits of a read-out address when the upper bits are changed from those of its preceding read-out address, the sense amplifiers are divided into some groups. A group of sense amplifiers for sensing and amplifying data of words including a word indicated by the read-out address is activated firstly and other groups are controlled to be activated a little delayed according to logic of lower bits of the read-out address when the upper bits are changed. Therefore, the peak value of the current consumption Can be decreased without any operational delay.

Error correction method for high speed communication

Abstract: PROBLEM TO BE SOLVED: To obtain an error correction system extended simply by allowing a transmitter side to add an output of an adder circuit and an output of a parity check circuit as redundant bits and allowing a receiver side to compare parity bits and redundant bits of a received signal. SOLUTION: At the transmitter side, an input signal is received and distributed to a coder circuit 2, an arithmetic circuit 3, and a multiplexer circuit 5. The output of the circuit 2 is given to a 2-element sum arithmetic circuit 4, in which a 2-element sum is calculated and the result is multiplexed by the circuit 5 and the result is inserted as the redundant bits in an SOH. Simultaneously the parity bits calculated by the circuit 3 are multiplexed by the circuit 5 and the result is written in the SOH. The output of the circuit 5 is demultiplexed by a demultiplexer circuit 6 to extract error correction coding bits and parity bits and they are given to a syndrome calculation circuit 8, a parity calculation circuit 9 and a memory 7. A comparator circuit 11 compares the output of the circuit 9 with the received parity check bits to locate an error frame. Then the stored signal in a memory 7 is corrected by a correction circuit 17 and the result is outputted. Thus, the correction system with simple and high extension performance is attained. COPYRIGHT: (C)1997,JPO

Circuit for removing energy dispersal in a data transmission

Abstract: The present invention relates to a circuit for removing energy dispersal in the transmission of a data packet, the circuit including a polynomial counter for supplying, at the transmission rate of the bits of the packet, correction bits to be respectively X-ORed with the bits of the packet. The correction bits are supplied to a series-to-parallel converter having its output combined with the successive packet parallel transmitted bits of the packet.

Compressing method of waveform data and digital data for musical sound control

Abstract: PURPOSE: To efficiently use a storage device. CONSTITUTION: When data compressed waveform data are to be stored in a storage device which has plural addresses and is able to store plural bit data in one address, the data are densely stored. Even though the number of bits of one data becomes less than the number of bits of one address by a compression, each data are compressed and densely stored. Alternatively, the waveform data, to which data value reduction processes are added, are densely stored in the storage device. Moreover, the maximum value of the effective number of bits of the waveform data for every segment is respectively detected, the number of bits of the waveform data of each segment is made same as the maximum value and the waveform data, in which the number of bits of each segment is made same, are densely stored in the storage device. This method is not only applicable to waveform data, but also applicable to other data for musical sound control.

A practical implementation of dynamic testing of an AD converter

Abstract: This paper presents a practical testing system which can measure the dynamic parameters such as effective bits (EB), signal to noise ratio (SNR), differential and integral nonlinearity (DNL and INL) of an AD converter. For practical implementation we propose a mixed frequency estimation algorithm with weighted least square method to estimate the EB. Furthermore we combine the spectral average method with frequency domain estimation to measure the SNR and use the histogram method to calculate the DNL and the INL. For practical purpose, we choose a logical analyzer as the high speed data acquisition device and a PC as the instrument controller. Two programmable signal generators with very low harmonic distortion are used for signal source of the ADC Testing. All the instruments are controlled by the PC through GPIB with a test software. Finally we apply the proposed test system and algorithm to measure the dynamic parameters of a real ADC (Datel ADC-HS12B). Results show that the proposed test system and methods are fast and accurate. Users can test the ADC automatically without worrying about the expensive testing instruments, interface problems and complex algorithms which may occur in other ADC testing systems.