Showing papers on "Effective number of bits published in 1997"

Coded modulation for digital storage in analog memory devices

Abstract: Digital data is stored in an analog memory device using coded modulation techniques. The memory device includes a number of memory cells, each capable of storing one of a number of different levels. A given set of b information bits to be stored in the memory device is first coded in a convolutional or block coder to generate a set of coded bits which includes more than b bits. The set of coded bits is then mapped to one or more corresponding levels, and the one or more levels are each stored in a separate cell of the memory device. In a one-dimensional embodiment, the coding may involve applying a rate 1/2 convolutional code to i least significant bits, i=1, 2, . . . , and mapping the resulting b+i coded bits to one of 2b+i distinct levels in a one-dimensional AM signal set. In embodiments of the invention which utilize multidimensional signal sets, a given set of bits is mapped to a signal in an m-dimensional signal set, with or without coding of the bits, and each of the m dimensions of the selected signal is then stored as a level in a separate cell of the analog memory device. The invention increases the storage capacity of the memory device for a given readout error probability, or alternatively improves the error probability for a given storage capacity. Readout performance may be further improved by using a multiple read-and-sum unit to generate a readout value for a given stored level based on a sum or average of several different readouts of the stored level.

An 8-GSa/s 8-bit ADC System

Abstract: We report on an analog to digital converter (ADC) system with 8 bit resolution and a sam le rate of 8 GSa/s. The system is composed of 2 thick-fh hybrid substrates, each holding a silicon bipolar ADC chip and a custom CMOS memory chip. Each ADC chip contains two differential track and hold circuits and two folding and interpolating 2 GSa/s flash digitizers. The custom memory chip accepts data at 2 GSa/s on each of two input ports, and stores the data in a 256 Kbit SUM. The ADC system uses time interleaving of 4 paths to reach 8 GSa/s and combines hardware dither with software calibration techniques to achieve 7.6 effective bits at low frequencies and 5.3 effective bits at 2 GHz input. Thick-film Hybrid

Circuit and method for multilevel signal decoding, descrambling, and error detection

Abstract: At least two level detectors compare a multilevel signal to respective prescribed voltage levels to produce corresponding streams of bits. These bit streams are repeatedly delayed in respective digital delay lines, and bits from the digital delay lines are output in parallel to multilevel decoder logic. The multilevel decoder logic converts the parallel bits into a plurality of corresponding two-level decoded bits and performs error detections for an invalid transition in the multilevel signal. The decoded bits may be descrambled and block decoded.

System for coding system

Abstract: A method and apparatus for coding an information signal are provided. In accordance with one aspect of the invention, the method includes the step of encoding all or a portion of the information signal with a first encoder to generate a first set of redundant bits (preferably r1 bits). The method further includes the step of passing a portion of (and possibly all) the information signal through a structured interleaver to generate an interleaved signal. The method then encodes all or a portion of the interleaved signal with a second encoder to generate a second set of redundant bits (preferably r2 bits). Finally, the method includes the step of concatenating the information signal, the first set of redundant bits, and the second set of redundant bits to form an encoded output signal. A significant aspect of the present invention is the use of a structured interleaver in the encoder. It has been found that the structured interleaver provides a low bit error rate, and a much shorter length (and thus delay) than random interleavers. The foregoing concept apply equally to multi-level coding, wherein a parallel concatenated code defined by a structured interleaver may be utilized as a constituent code in a multi-level encoder.

Method and apparatus of providing bit count integrity and synchronous data transfer over a channel which does not preserve synchronization

Abstract: Synchronization and bit count integrity of a synchronous data stream is preserved end to end even as it is transmitted via a medium which does not preserve the synchronous nature of the synchronous data stream. A terminal equipment unit (100) produces a constant rate bit stream which is provided to a communications unit (110). The communications unit (110) produces a first data frame comprising a first set of bits from the constant rate bit stream and a first length field value. A second data frame is produced which comprises a second set of bits from the constant rate bit stream and a second length field. A third data frame is produced which comprises a third set of bits from the constant rate bit stream and a third length field value. The first, second, and third data frames are transmitted to a base unit (118) which places the first set of bits from the first frame into a queue (150). A set of fill bits equal to the maximum number of bits contained in any frame is then placed into the queue (150). The base unit (118) then determines the number of bits in the second set of bits of the third data frame, based on the first length field value and the third length field value. The base unit (118) overwrites excess fill bits in the queue (150) with the third set of bits. The number of excess fill bits is equal to the difference between the maximum possible number of bits which may be contained in any frame and the number of bits in the second set of bits.

Non-linear characteristic correction apparatus and method therefor

Abstract: A non-linear response correction apparatus and method reduce look up table size and output error. In one embodiment, a range of an N-bit input signal is split into two or more sectors, based on a gradient of a non-linear correction curve and an allowable error, and then a N-bit input signal is divided into U upper bits and D lower bits where U and D depend on which sector contains the input signal. First and second look up tables read first and second data stored therein, respectively, using the upper bits of the digital signal as an address. The first data is the difference between a corrected signal and the input signal, and the second data is the gradient of the corrected signal with respect to the gradient of the input signal. The second data read from the second look up table is multiplied by the lower bits, and the first data read from the first look up table is added to the upper bits. The sum is added to the product to produce an N-bit digital corrected signal that compensates for the non-linear characteristics.

Nonlinearity of a data-acquisition system with interleaving/multiplexing

Abstract: The study of differential nonlinearities (DNL) and integral nonlinearities (INL) of a high-speed data acquisition system using interleaving/multiplexing yields a theoretical expression for both errors, showing that they are smaller than the DNL and INL errors for each analog-to-digital converter (ADC) channel. Both experimental and computer-simulated data reveal very good agreement with the theoretical results. It is also shown that for this type of interleaved acquisition system, that has a time-dependent transfer characteristic, the effective number of bits cannot be evaluated via histogram testing.

High resolution ADC system

Abstract: We have developed and verified experimentally a novel high-resolution superconducting ADC architecture based on phase modulation/demodulation principle and implemented in RSFQ logic. We have demonstrated an ADC chip providing full implementation of this architecture, including on-chip decimation filter and multiple-channel synchronizer. We have also developed a digital ADC evaluation system consisting of an interface electronics block converting the low-voltage ADC output to standard TTL form at multi-MHz sampling rate, and a computerized test station performing data acquisition, processing and display in real time. Using this system we have demonstrated that for low-frequency (kHz) signals our ADC chips possess linearity in excess of 16 bits with Spur-Free Dynamic Range over 108 dB, which is an important benchmark for any high-resolution ADC technology.

Methods and systems for communicating information using separable modulation constellations

Abstract: A source set of bits is modulated according to a modulation constellation to produce a modulated communications signal, wherein the modulation constellation preferably is Gray-coded and is selected to provide a communications signal from the source set of bits such that real and imaginary components of the communications signal map to mutually exclusive first and second subsets of the source set of bits. The modulated communications signal is communicated over a communications channel. Soft information for the first subset of bits of the source set of bits is determined from a real component of a product of a channel transfer characteristic and the communicated modulated signal, the channel transfer characteristic characterizing communications over the communications channel. Soft information for the second subset of bits of the source set of bits is determined from an imaginary component of the product of the channel transfer characteristic and the communicated modulated signal. Iterative aspects for higher-order modulation and demodulation are also provided. Related systems and apparatus are also described.

Coding method and apparatus

Abstract: A parallel concatenated coder (20) outputs a sequence of data sets in which earlier data sets contain data bits (d) and non-interleaved parity bits (p) without interleaved parity bits (q), while later data sets include the interleaved parity bits (q). Each data set is modulated as one symbol. The output format partially overcomes the delay incurred by interleaving the parity bits (q), with a substantially even distribution of data and parity bits in the sequence of data sets. The delay may be reduced further by interleaving with an index constraint.

Fixed wireless loop system having baseband combiner predistortion summing table

Abstract: Disclosed is a method for generating I/Q waveforms for transmission over a CDMA radio channel. The method includes steps of (a) summing, for each of a plurality N of channels, the state of I bits to form an Isum value having a sign bit, the state of Q bits to form a Qsum value having a sign bit, and a total number of active channels to form a channel sum value; (b) applying the Isum value and sign bit, the Qsum value and sign bit, and the channel sum value to an input of a multiplexer; and (c) time multiplexing the inputs to generate first and second sets of output bits. The first set of output bits includes a subset of the Isum value bits, a subset of the Qsum value bits, the I sign bit, and the channel sum value bits. The second set of output bits includes the subset of the Isum value bits, the subset of the Qsum value bits, the Q sign bit, and the channel sum value bits. A next step of the method sequentially applies the first and second sets of output bits to a lookup table memory device for sequentially outputting an I value and a Q value for application to a digital to analog converter for generating I/Q waveforms that are predetermined to reduce transmission power and distortion. In the preferred embodiment of this invention the lookup table memory uses the LSB of the channel sum value as the LSB of the I value and the LSB of the Q value.

Data communications systems and methods using interspersed error detection bits

Abstract: A communication system and method for communicating data bits includes generating error detection bits for interspersing within a sequence of data bits to be transmitted to provide a message to be transmitted. The interspersed data bits may be dependent on the data bits or determined independent of the data bits. The message to be transmitted is convolutionally encoded and transmitted through a communications medium. The received message is convolutionally decoded by a convolutional decoder which is operably connected to an error indication logic circuit. The interspersed error detection bits may be used to detect an uncorrected error in transmission or to constrain the convolutionally decoding to provide an improved error correction operation based on the determinate values of the interspersed error detection bits.

Parallel variable bit encoder

Abstract: A data segmentation circuit is disclosed for use in DS3/STS-1 mapping. The data segmentation circuit uses a circular data buffer to store data for mapping. A recirculating barrel shifter is used for extracting data from within the buffer. A counter moves the barrel shifter window zero, one, five, or eight bits to align the barrel shifter output as necessary to extract a next datum for a next payload envelope location. Data stuffing is then performed. Control circuitry for providing throttling and bit stuffiing as required in an STS-1 information payload is disclosed.

Method of testing an analog-to-digital converter

Abstract: Only the value of the least-significant bit, or of some of the less-significant bits is used in order to test an analog-to-digital converter in an integrated circuit. The information concerning the differential and the integral non-linearity can be determined from the values of said less-significant bit. Furthermore, the functionality of the analog-to-digital converter is tested by counting the number of changes of the least-significant bit and by comparing this number with the value formed by the other bits.

Method, circuit and apparatus for preserving and/or correcting product engineering information

Abstract: A method, circuit and apparatus is provided for preserving and/or correcting product engineering information. Non-volatile storage devices reserved for receiving product engineering bits can either be contained in at least three separate storage locations spaced from each other across the integrated circuit or, alternatively, be contained in a single storage location area with error correction bits and/or words added to that location. In the first instance, redundant product engineering bits are written to each storage location. Product engineering bits read from a majority of those locations which have identical values are deemed valid. The addition of extra bits and/or words can be combined with the possibly defective product engineering bits to correct errors in those bits. Using redundancy to correct errors caused by charge loss or charge gain within previously stored product engineering values proves a beneficial outcome since testing the product engineering bit locations is not necessarily a viable solution. The product engineering bit locations may be programmed well before test patterns can be written to and read from those locations. Further, the uniquely programmed product engineering bits may unduly be lost during normal assembly of die into an integrated circuit package.

System for detecting open circuits with a measurement device

Abstract: A method for determining whether a circuit under test is open is presented. A digital-to-analog converter is dithered to generate a known signal. This known signal is summed with an external attenuation signal which is brought into the system from a probe on the circuit under test. This summation is then measured by an analog-to-digital converter (ADC). If the known signal is not attenuated by the probe (i.e., the ADC measures essentially the known signal), we can conclude that the circuit is open.

Digital coding process for transmission or storage of acoustical signals by transforming of scanning values into spectral coefficients

Abstract: A digital coding process for the transmission and/or storage of acoustical signals and, in particular, of musical signals, in which N scanning values of the acoustical signals are transformed into M spectral coefficients. The M spectral coefficients are quantized in the first step. Following encoding, the number of bits required for representation is checked utilizing an optimum encoder. If the number of bits is greater than the prescribed number of bits, quantization and encoding is repeated in further steps until the number of bits required for representation does not exceed the prescribed number of bits, whereby the required quantization level is transmitted or stored in addition to the data bits. Transmission and/or storage of acoustical signals and, in particular, of musical signals is accordingly possible without subjective diminishment of quality of the musical signals while reducing the data rates by factor 4 to 6.

Data transfer method and transceiver equipment

Abstract: The invention relates to a data transfer method and a transceiver equipment in a digital mobile network, in which the information to be transmitted is channel coded for the transmission. In the current 4800 bit/s data transfer service of the mobile network, information bits to be transmitted are block coded (31) to a block of 152 bits, which block is convolutional coded (32) at the ratio 1/3 into a block of 456 bits. The block of 152 bits contains, besides the information bits, fill bits having no effect on the error correction performance. These fill bits are overhead capacity in the nominal bit rate of the radio interface traffic channel point of view. In the present invention, this overhead capacity is used for supporting a new 7200 bit/s user rate. Then the number of information bits is increased and the number of fill bits is decreased in a 152 bit frame (62) in such a way that the user rate before block coding (31) increases, but the data rate before convolutional coding (32) remains unchanged. Consequently, the same 1/3 convolutional coding can be used for the 7200 bit/s user rate as is used for the 4800 bit/s user rate.

Consideration for Folding/Interpolation ADC with SiGe HBT

Abstract: This paper describes the design and performance of a high-speed 6-bit ADC using SiGe HBT for measuringinstrument applications. We show that the GummelPoon model suffices for SiGe HBT modeling and then we describe that the folding/interpolation architecture as well as simple, differential circuit design are suitable for ADC design with SiGe HBT. Measured results show that the nonlinearity of the ADC is within fl/2LSB, and the effective bits are 5.2 bits at an input frequency of 100MHz and 4.2 bits at 200MHz with 768MS/s. We also describe some design issues for folding/interpolation ADC.

Muti-bit successive-approximation analog-to-digital converter with improved conversion speed

Abstract: The subject invention relates to a type of multi-bits successive-approximation ADC to convert analog signals into a N-bits digital output code, wherein N is the number of bits of output code. The ADC includes (a) an input sample/hold circuit that takes the sample of analog input signals during the first half of clock cycle, and maintains the analog input signals after the sampling and during a conversion process. The ADC also includes (b) a reference voltage generator, to produce different reference voltages, (c) CLOCK pulse generation circuitry to continuously produce CLOCK pulse signals, (d) several comparators for comparison of the sampled input signals with a rough reference voltage to produce a rough digital output code. The ADC applies a temperature scale to roughly estimate the sampled analog input signals, this to be completed in a second half of the CLOCK cycle. The ADC further includes (e) a digital thermometer decoder producing a signal output of N bits, and (f) and output code data recording device to provide the output of complete signal data after conversion has been completed.

New Dynamic Test Methods for Determination of Nonlinearity and Effective Resolution of A/D Converters

Abstract: This paper presents new methods for determination of differential nonlinearity (DNL) and effective resolution also known as Effective Bits (EB) of an A/D converter. DNL is determined by deviation of histogram of test ADC from histogram of ideal ADC generated through software. Modifications are applied in the standard histogram approach for more accurate estimation of Integral nonlinearity (INL). Combination of histogram and least square error minimization techniques is used for determination of EB of an A/D converter. Computer simulations show that proposed methods give better results as compared to the histogram method. Limitations of standard histogram technique for determination of these parameters are also reported. Effects of uncertainties of slope and intercept of best fit transfer characteristics of the ADC on EB are also analyzed.

A 1 GS/s, 11-b track-and-hold amplifier with <0.1 dB gain loss

Abstract: A track-and-hold amplifier for use in high-speed ADCs was implemented in a production AlGaAs/GaAs HBT process. Under Nyquist conditions, the fabricated ICs showed 11 effective number of bits (ENOBs) at 1 GS/s and >12 ENOBs at 800 MS/s. The large signal gain loss of these ICs was measured to be below 0.1 dB.

Method and apparatus in a communication receiver for compensating for channel amplitude and phase distortion

Abstract: A radio signal is digitized and filtered to derive a digitized pilot signal (210) modulated by channel amplitude and phase distortion. A numerator and a denominator are formed for dividing the digitized radio signal (208) by the digitized pilot signal, the numerator and the denominator requiring a first predetermined number of bits per sample. The bits of the numerator and the denominator are shifted (518) by equal amounts until a highest order bit of one of the numerator and the denominator is non-zero. A second predetermined number of highest order bits of the numerator are divided (524) by the second predetermined number of highest order bits of the denominator in a divider utilizing less than the first predetermined number of bits, to generate a channel compensated radio signal (536) having a minimum number of bits that can accommodate a predetermined maximum dynamic range.

Method of adding two binary numbers and binary adder used therein

Abstract: An adder has a carry signal generation block for producing carry generation signal bits representative of carry bits resulted from augend signal bits and addend signal bits and carry propagation signal bits representative of carry bits resulted from the augend signal bits, the addend signal bits and the carry bits supplied from lower-digits, a carry propagation block responsive to control signal bits for dividing the adder into partial adders and having propagation stages for producing carry signal bits from the carry generation signal bits, the carry propagation signal bits and the control signal bits, and a sum generation block for producing sum signal bits from the carry propagation signal bits, the control signal bits and the carry signal bits, and is divisible into an arbitrary number of partial adders without increase the stages of a critical path.

Time diversity communication method and communication device

Abstract: In time diversity communication system, loss of data or generation of incorrect data may occur due to, for example, the shadow effect. In the present invention, on the transmission side, an interlaced signal is generated in which the input digital signal string is combined with the same signal string delayed by n bits, k redundancy bits are added to every m bits of this signal, the signal is divided into blocks of (m+k) bits, an interleaving process is executed for every j blocks in which unique words are added, following which the signal is transmitted. On the receiving side, unique words are detected, a de-interleaving process is performed, and a check is made for the presence of error signals. The delayed and non-delayed signals are next separated from the decoded data, and depending on the state of the signals, the desired signal is selected at selector 33 and outputted. A conformity judgment circuit judges conformity with the separated signal determined to be effective using effective gate signals indicating the effectiveness or ineffectiveness of decoded data, performs switching control of the separated signals, and monitors synchronization.

Bit reduction of dct basis for transform coding

Abstract: Extensive research has been carried out on transform coding using the discrete cosine transform (DCT) for compression of digital video data. Improvement of the video quality has been brought about by an increased number of pixels, such that a reduction of the time required for coding per pixel is highly desirable. When the multiplier coefficients in the coding operation or the values of the basis coefficients of the DCT are expressed as binary numbers, it is possible to reduce the operating time and simplify the process by using as few bits as possible. It is necessary to consider the constraint that the picture quality of the reconstructed video image should not be degraded by the reduction of the number of bits. In this paper, it is shown that the number of bits of the basis coefficients can be reduced under this constraint if quantization of the transform coefficients is taken into account. Also, the limiting value of the decrease of the number of bits in specific coding examples such as JPEG is determined. Finally, it is confirmed that the quality of the reconstructed video image changes very little even if the basis coefficients are represented by fewer bits than in previous schemes, provided that the reduction is within the limit presented in this paper. © 1997 Scripta Technica, Inc. Electron Comm Jpn Pt 1, 80(8): 81–91, 1997

Multiported register file for burst mode coefficient updating

Abstract: Multiported register files used for storing coefficients in adaptive FIR are improved upon by implementing a split memory architecture that has the ability to separately control the least significant bits and the most significant bits of coefficient values that are stored in the filter. When the filter is operated to use so-called "burst mode" updating, the updating circuitry of the filter can be disabled and only the most significant bits of the coefficients are read out from the multiported register file while the least significant bits remain unchanged. This conserves power without sacrificing precision, since only certain ones of the bits of the coefficients are used in the multiplication of the sample. In addition, when only the most significant bits of the coefficients are being cycled through the register filter, any changing bits are prevented from being supplied to the updating circuit, so that the updating circuit performs no computation at all, rather than performing one that is discarded. Advantageously, using such improved multiported register files, adaptive FIR filters can be constructed which operate with lower power consumption.

Multicolor display control circuit and method for liquid crystal display

Abstract: A dither circuit and method for reproducing a multicolor image includes a latch having input terminals for 8 input data bits and clock signal, and output terminals for six high bits and two low bits of the input-data bits; a dither timing generator having input terminals for a horizontal sync signal, a vertical sync signal and a clock signal and output terminals for a first dither timing bit and the second dither timing bit, wherein the first dither timing bit is toggled according to each cycle of the horizontal sync signal and the second dither timing bit is toggled according to each cycle of the vertical sync signal; a dither data controlierhaving input terminals for the two low bits, the first and the second dither timing bits and an output terminal for applying four dither data bits generated using the two low bits and the first and the second dither timing bits sequentially; and an adder having an input terminal for the dither data bit and six high bits, and output terminals for six output data bits.