Showing papers on "Effective number of bits published in 2003"

A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC

Abstract: A 10-bit 80-MS/s analog-to-digital converter (ADC) with an area- and power-efficient architecture is described. By sharing an amplifier between two successive pipeline stages, a 10-bit pipeline is realized using just four amplifiers with a separate sample-and-hold block. The proposed feedback signal polarity inverting (FSPI) technique addresses the drawback of the conventional amplifier sharing technique. A wide-swing wide-bandwidth telescopic amplifier and an early comparison technique with a constant delay circuit have been developed to further reduce power consumption. The ADC is implemented in a 0.18-/spl mu/m dual-gate-oxidation CMOS process technology, achieves 72.8-dBc spurious free dynamic range, 57.92-dBc signal-to-noise ratio, 9.29 effective number of bits (ENOB) for a 99-MHz input at full sampling rate, and consumes 69 mW from a 3-V supply. The ADC occupies 1.85 mm/sup 2/.

A new class of asynchronous A/D converters based on time quantization

Abstract: This work is a contribution to a drastic change in standard signal processing chains. The main objective is to reduce the power consumption by one or two orders of magnitude. Integrated Smart Devices and Communicating Objects are application domains targeted by this work. In this context, we present a new class of Analog-to-Digital Converters (ADCs), based on an irregular sampling of the analog signal, and an asynchronous design. Because they are not conventional, a complete design methodology is presented. It determines their characteristics given the required effective number of bits and the analog signal properties. it is shown that our approach leads to a significant reduction in terms of hardware complexity and power consumption. A prototype has been designed for speech applications, using the STMicroelectronics 0.18-/spl mu/m CMOS technology. Electrical simulations prove that the factor of merit is increased by more than one order of magnitude compared to synchronous Nyquist ADCs.

A wide input bandwidth 7-bit 300-MSample/s folding and current-mode interpolating ADC

Abstract: A 7-bit Nyquist folding and interpolating analog-to-digital converter (ADC) that converts at 300 MSamples/s is presented. Using current-mode signal processing techniques for analog preprocessing and a front-end sample-and-hold, the proposed 7-bit folding and interpolating ADC yields a wide input bandwidth up to 60 MHz with six effective number of bits. The ADC consumes 200 mW from a 3.3-V power supply. The chip occupies 1.2 mm/sup 2/ active area, fabricated in 0.35-/spl mu/m CMOS.

Photonic A/D conversion using low-temperature-grown GaAs MSM switches integrated with Si-CMOS

Abstract: By linking the unique capabilities of photonic devices with the signal processing power of electronics, photonically sampled analog-to-digital (A/D) conversion systems have demonstrated the potential for superior performance over all-electrical A/D conversion systems. We adopt a photonic A/D conversion scheme using low-temperature (LT)-grown GaAs metal-semiconductor-metal (MSM) photoconductive switches integrated with Si-CMOS A/D converters. The large bandwidth of the LT GaAs switches and the low timing jitter and short width of mode-locked laser pulses are combined to accurately sample input frequencies up to several tens of gigahertz. CMOS A/D converters perform back-end digitization, and time-interleaving is used to increase the total sampling rate of the system. In this paper, we outline the development of this system, from optimization of the LT GaAs material, speed and responsivity measurements of the switches, bandwidth and linearity characterization of the first-stage optoelectronic sample-and-hold, to integration of the switches with CMOS chips. As a final proof-of-principle demonstration, a two-channel system was fabricated with LT GaAs MSM switches flip-chip bonded to CMOS A/D converters. When operated at an aggregate sampling rate of 160 megasamples/s, the prototype system exhibits /spl sim/3.5 effective number of bits (ENOB) of resolution for input signals up to 40 GHz.

Signaling dependent adaptive analog-to-digital converter (ADC) system and method of using same

Abstract: An adaptive analog-to-digital converter (ADC) system ( 100 ) includes an automatic gain control (AGC) controller ( 101 ) for receiving both in-band and out-of-band signals from a radio frequency (RF) receiver and producing an AGC control signal therefrom. A digital signal processor (DSP) ( 103 ) is then used for interpreting the AGC control signal and providing an adjustment signal to an ADC ( 105 ). The ADC ( 105 ) uses the adjustment signal to dynamically control efficiency of the ADC system 100 by adjusting bit resolution, reference capacitance and bias based upon the RF signal received and desired protocol requirements presented to the AGC controller ( 101 ).

A 69 mW 10 b 80 MS/s pipelined CMOS ADC

Abstract: A 10 b 80 MHz pipelined ADC with an active area of 1.85 mm/sup 2/ is realized in a 0.18 /spl mu/m dual gate oxidation CMOS process and achieves 72.8 dBc SFDR, 57.92 dB SNR, and 9.29 ENOB for a 100 MHz input at full sampling rate. The ADC shares an amplifier between two successive pipeline stages in order to achieve a power consumption of 69 mW at 3 V.

Secure hardware random number generator

Abstract: A random number generator comprises random number generation circuitry to generate and output random bits. The random number generator comprises interface circuitry to receive and store random bits output by the random number generation circuitry and to output random bits. The interface circuitry prevents outputting the same random bits more than once.

A 5-b 10-Gsample/s A/D converter for 10-Gb/s optical receivers

Abstract: A 5-bit 10-Gsample/s A/D converter (ADC) is fabricated in a SiGe BiCMOS process to digitally compensate the signal distortion in a 10-Gb/s optical receiver. A fully differential, flash-type ADC has a wideband track-and-hold amplifier to mitigate the timing skew, followed by high-speed comparators with very small metastability error. It achieves a 4.1 effective bits at low input frequencies and 2.8 effective bits at full-scale 4.9-GHz input signal at 10-Gsample/s.

Architecture for an algorithmic analog-to-digital converter

Abstract: An algorithmic analog-to-digital converter (ADC) includes a sample-and-hold circuit and an ADC processing unit operating in parallel and sharing a single operational amplifier. The ADC processing unit includes an MDAC with a switched capacitor topology and a sub-ADC. The ADC processing unit is clocked by an internal clock that is N times faster than the sample-and-hold clock. Each cycle is further sub-divided into two phases. During one phase the capacitors are coupled to a residue or sampled voltage provided by the MDAC, and during another phase the capacitor are coupled to a reference voltage determined by the switch control signals generated by the sub-ADC. A set of data bits is generated by the ADC processing unit during each ADC clock cycle. The N sets of data bits are added to generate the digital output stream.

Relationship between ADC performance and requirements of digital-IF receiver for WCDMA base-station

Abstract: The recent rapid development of digital wireless systems has led to the need for multistandard, multichannel radiofrequency (RF) transceivers. The paper presents the relationship between the performance of a bandpass-sampling analog-to-digital converter (ADC) and the requirements of a digital intermediate-frequency receiver for a wideband code-division multiple-access (WCDMA) base-station. As such, the ADC signal-to-noise ratio (SNR), the derivation of the receiver sensitivity using the SNR/spurious free dynamic range (SFDR) of the ADC, the effect of the ADC clock jitter and receiver linearity, plus the relationship between the receiver IF and the ADC sampling frequency are all analyzed. As a result, when a WCDMA base-station receiver has a data rate of 12.2 kbps, bit error rate (BER) of 0.001, and channel index, k, of 5 (sampling frequency of 122.88 MHz and IF of 92.16 MHz), the performance of a bandpass-sampling ADC was analytically determined to require a resolution of 14 bits or more, SNR of 66.6 dB or more, SFDR of 86.5 dBc or more, and total jitter of 0.2 ps or less, including internal ADC jitters and clock jitters.

System and method for transmitting audio or video data using multiple levels of protection

Abstract: A data transmission and distribution system that includes a series of payloads (200), where each of the payloads is formed from bits of audio or video information (252), and where different levels of protection are applied to different sets of bits in each payload. The system divides the bits associated with each payload into high priority bits (210) and low priority bits (220) and forms a group of check bits (256) for each payload by applying an error correction algorithm to the high priority bits in the payload. The system also forms each payload from a first set of the high priority bits (210), the check bits (256), the low priority bits (220) and a redundant set of the high priority bits and the check bits (230) and transmits the payloads formed from the first set of the high priority bits, the check bits, the low priority bits and the redundant set of the high priority bits and the check bits (200).

Impact of capacitor dielectric relaxation on a 14-bit 70-MS/s pipeline ADC in 3-V BiCMOS

Abstract: In this paper, phenomena of charge absorption and relaxation in the plasma enhanced chemical vapor deposition (PECVD) silicon nitride dielectric (Si/sub 3/N/sub 4/) used in the capacitors of a 45-GHz f/sub T/, 0.4-/spl mu/m L/sub min/ SiGe BiCMOS are observed and interpreted. When such capacitors are used to design a pipelined 14-bit 70-MS/s switched-capacitor analog-to-digital converter (ADC), dielectric relaxation is identified as the cause of 8-LSB-wide gaps in the integral nonlinearity, which leads to the degradation of the converter performance even at low frequencies. The effect has been analyzed via Matlab behavioral simulations and SPICE circuit simulations. Ad-hoc experimental tests aimed at detecting residual amounts of charge left in the capacitors as a memory of previous states have been also carried out. After low-density low-pressure chemical vapor deposition (LPCVD) oxide capacitors (SiO/sub 2/) are introduced in the process, a new ADC test chip delivers 72.5-dBFS SNR, 82-dBc SFDR, 11.7-bit ENOB at 70 MS/s and 1-MHz input. The circuit features a die size of 5.3 /spl times/ 5.3 mm/sup 2/ and dissipates 1 W from the 3.3-V supply.

Nonlinear distortion compensating circuit

Abstract: This invention relates to a nonlinear distortion compensating circuit in which a digital value expressing the amplitude of an input signal is divided into upper and lower bits, only the upper bits are input to an address in a first memory, a value obtained by adding 1 to the upper bits is input to an address in a second memory, or, an interpolation circuit to which the upper bits are input inputs the upper bits to a first memory storing data corresponding to an even-numbered address and a second memory storing data corresponding to an odd-numbered address, and performs interpolation by adding outputs from the first and second memories by weighting these outputs in accordance with a value expressed by the lower bits, and the input signal is multiplied by the obtained value. In this arrangement, an interpolation circuit output based on the outputs from the first and second memories is an orthogonal coordinate expression (a combination of a real part and imaginary part) or a polar coordinate expression (a combination of an amplitude and phase).

(146,130) error correction code utilizing address information

Abstract: A method of detecting double-symbol errors and correcting single-symbol errors in a data stream being transmitted in a computer system, e.g., from a memory array to a memory controller. The method includes decoding the data stream which was encoded using a logic circuit which had, as inputs, the data being sent and two address parity bits derived from the system address of the data. Data retrieved from the wrong address can be detected by this code. The logic circuit is described by a parity-check matrix for this ( 146,130 ) code comprising 128 data bits, 16 check bits, and 2 address parity bits. Although the symbol width of the code is four bits, the code can also be used effectively in memory systems where the memory chip width is eight bits.

Technique for improved linearity of high-precision, low-current digital-to-analog converters

Abstract: A high-precision high-linearity digital-to-analog converter (DAC) and a method for converting a digital input signal having N bits to a substantially equivalent analog current output signal is presented. The DAC segments the digital input signal bits into groups separate processing. The invention includes a first current-steering digital-to-analog converter configured to receive a first group of i input signal bits and a first reference current to produce a first current signal. A second current-steering digital-to-analog converter is configured to receive a second group of j input signal bits and the first reference current to produce an intermediate current signal. The intermediate current signal is scaled down by a factor of 2 j to produce a second current signal. A summing circuit sums at least the first and second current signals to produce an analog current signal representative of the digital input signal value.

Method and device for adaptive quantization of soft bits

Abstract: A method and device for adaptive quantization of soft bits includes numerically sorting soft bits of an external data block (200) having a log likelihood ratio distribution of the soft bits, each of the soft bits having a value, the sorted soft bits having extreme values, determining two point values in the log likelihood ratio distribution of the data block (300) respectively located at a clipping distance away from each extreme value of the sorted soft bits, defining an adapted quantization range with a half-length equal to half of a difference between the two point values or with a half-length equal to a larger of two absolute values of the two point values (600B), and placing each of the soft bits within a respective sub-range of the adapted quantization range (700). An adapted quantization range is determined whenever the log likelihood ratio distribution of the data block changes.

Method for rate matching

Abstract: The invention relates to a method for rate matching a number of input bits in a time interval to a fixed number of output bits in the time interval, - whereby said input bits consist of a set of at least two different bit classes, each of the classes having a certain number of bits in the time interval,- whereby the rate matching is performed in two rate matching stages ,- whereby the first rate matching stage operates only on a selection out of the set of different bit classes, thus establishing a proportion between the number of bits of the different classes,- and the second rate matching stage operates on all bit classes such, that said proportion is exactly or approximately maintained after the second rate matching stage and the fixed number of output bits consisting of bits of the different bit classes is achieved .

High-speed high-resolution ADC for precision measurements

Abstract: A measurement device such as a DMM may include four basic units—an analog circuit path, an analog to digital converter (ADC), a digital filter, and an RMS computation unit. The four basic units may be operable to multiplex or to process one or more of the plurality of channels at the same time. The analog circuit path may include the necessary circuitry for the plurality of channels to couple to one or more analog signals. The analog circuit path may couple to the ADC. The ADC may be operable to receive the one or more analog signals from the analog circuit path and convert it to one or more digital signals. The ADC may include a cascaded ADC, which may include a first ADC and a second ADC. The first and the second ADC and may be able to convert analog data to digital data during a cycle. In one embodiment, the first ADC may generate a conversion result and an error signal. The second ADC may be operable to receive the error signal, digitize the error signal, and process the error signal, thus performing noise cancellation. A summation operation may combine the data from the first ADC and the processed data from the second ADC. The cascaded ADC may consist of a continuous-time 1-bit sigma-delta modulator followed by a SAR ADC. Digital output from sigma-delta modulator may be weighted and summed with the output of the SAR ADC in an FPGA.

Analysis of mismatch noise in randomly interleaved ADC system

Abstract: Time interleaved A/D converters (ADC) can be used to increase the sample rate of an ADC system. However, a problem with time interleaved ADC is that distortion is introduced in the output signal due to various mismatch errors between the ADC. One way to decrease the impact of the mismatch errors is to introduce additional ADC in the interleaved structure and randomly select an ADC at each sample instance. The periodicity of the errors is then removed and the spurious distortion is changed to a more noiselike distortion, spread over the whole spectrum. In this paper, a probabilistic model of the randomly interleaved ADC system is presented. The noise spectrum caused by gain errors is also analyzed.

Method and apparatus of system offset calibration with overranging ADC

Abstract: A method and apparatus for system offset calibration using an overranging ADC is provided. The overranging ADC is configured to convert an analog signal into an intermediary digital signal. The conversion range of the overranging ADC is extended beyond the full dynamic range of the ADC system. The intermediary digital signal has more bits than the digital output signal. A digital fine offset adjustment circuit is configured to provide the digital output signal by digitally subtracting a fine offset from the intermediary digital signal and decoding the intermediary digital signal. The digital output signal has approximately no offset, and has approximately no loss in dynamic range.

Column address path circuit and method for memory devices having a burst access mode

Abstract: Column addresses are generated by a burst controller that includes respective latches for the three low-order bits of a column address. The two higher order bits of the latched address bits and their compliments are applied to respective first multiplexers along with respective bits from a burst counter. The first multiplexers apply the latched address bits and their compliments to respective second multiplexers during a first bit of a burst access, and bits from a burst counter during the remaining bits of the burst. The second multiplexers are operable responsive to a control signal to couple either the latched address bits or their compliments to respective outputs for use as an internal address. The control signal is generated by an adder logic circuit that receives the two low-order bits of the column address. The adder logic circuit processes the column address bits at the same time the address bits are being coupled through the second multiplexer to the first multiplexer as a function of the correct relationship between the internal address bits and the external address bits.

ADC testing using interpolated fast Fourier transform (IFFT) technique

Abstract: An ideal transfer characteristic of an analogue-to-digital converter (ADC) is simulated and an arbitrary nonlinearity error is introduced. A full-scale sine wave is also simulated and applied to ADC input. The interpolated fast Fourier transform (IFFT) technique is used to determine accurately fundamental and other harmonics in the output spectrum of the ADC. The signal-to-noise ratio and the effective number of bits (ENOB) are computed on the basis of FFT and IFFT for different resolutions of ADC and test conditions. The effects of rectangular and Hanning time window functions on the determination of frequency components are reported. The proposed method of dynamic testing of the ADC is useful for users as well as manufacturers.

Analog-to-digital converter with digital signal processing functionality to emulate many different sample frequencies, resolutions, and architectures

Abstract: A system for emulating characteristics of a plurality of analog-to-digital converter (ADC) architectures in the conversion of an analog signal to a digital signal. The system comprises a flash ADC for sampling the analog signal and outputting a digital representation of a sample of the analog signal, a digital-to-analog converter (DAC) for supplying the reference values to the flash ADC, and a digital signal processor (DSP) for processing the digital representation of the sample and outputting the digital signal. The digital representation is based on a comparison of the sample to reference values and comprising a number of bits of resolution. The DSP is configured to send a modifiable control signal defining the reference values to the DAC.

Multi-bit continuous time sigma-delta ADC

Abstract: A multi-bit continuous-time sigma-delta analog-to-digital converter (10) provides a digital output signal as a digital representation of an analog input signal. The converter performs several functions in providing the digital output signal. First, the converter provides an analog summing signal (20) indicative of a summation of the analog input signal and an analog feedback signal (50). Second, the converter provides a first set of bits as a digital representation of the analog summation signal. Third, the converter provides a second set of bits as a digital representation of a periodic sampling of the first set of bits. Fourth, the converter provides the analog feedback signal as analog representation of the second set of bits. Fifth, the converter outputs the first set of bits or the second set of bits as the digital output signal.

Fan control system with improved temperature resolution

Abstract: A system and method for increasing resolution of pulse width modulated (PWM) signal duty cycle calculations in a fan speed control system operating to control rotational speed of at least one fan. The method may comprise obtaining a temperature reading from a first temperature sensor in the fan speed control system during a first time period. The temperature reading has resolution of a first number of bits. A portion of the first number of bits is selected for calculating a PWM signal duty cycle with the resolution of the first number of bits in the temperature reading using only the portion of the first number of bits and zone parameters associated with the first temperature sensor. The PWM signal duty cycle may then be converted into a PWM signal that may be provided to the at least one fan.

A 1.8V 100mW 12-bits 80Msample/s two-step ADC in 0.18-/spl mu/m CMOS

Abstract: The design, optimisation, efficiency and measurement results of the two-step 12-bits analogue-to-digital converter fabricated in a 0.18-/spl mu/m CMOS process are presented. Performance of 66.3dB SNR, -73.1dB THD, 78.4dB SFDR, 10.5 ENOB at 60 MS/s and 9.7 ENOB at 80 MS/s has been obtained using a mixed-signal chopping and calibration algorithm, drawing less than 100 mW from 1.8V supply for both analogue and digital core. The ADC has been fabricated in a single-poly 5-metal 0.18-/spl mu/m CMOS process and measures 0.67 mm/sup 2/.

Method and apparatus for estimating and controlling the number of bits output from a video coder

Abstract: A method and apparatus is provided for estimating the number of bits output from a video coder given a known spatial data content, G={g 1 , . . . , g N }, of a group of luminance and chrominance blocks, and a known coding mode, d, where d represents the index of said coding mode. The method comprises the steps of extracting a significant part of the spatial data content, G, in relation to the coding mode, d, to yield a feature vector F, the feature vector representing statistics and signal components of the luminance and chrominance data of the luminance and chrominance blocks; mapping the feature vector to yield a class index, c, for said respective group of luminance and chrominance blocks; mapping the class index, c, in relation to a quantization parameter, q, where the quantization parameter controls the scale of the bin size of the quantizer applied to the transform coefficients, to yield an estimated number of quantization bits for the group of luminance and chrominance blocks; and determining an estimated total number of coding bits for the group of luminance and chrominance blocks from the combination of the estimated number of quantization bits and an estimated number of overhead bits, wherein the overhead bits represent the additional bits expended to represent respective portions of the bitstream.

A 75mW 10bit 120MSample/s parallel pipeline ADC

Abstract: This paper describes a low-power high-speed parallel pipeline ADC. The thorough use of digital calibration and the pseudo-differential pipeline ADC architecture allow to realize the low-power design of high-speed ADC's. Capacitor mismatch, gain and offset errors are measured by technique using INL plot, without any modification to ADC core. A prototype ADC with the error correction logic is fabricated in 0.3/spl mu/ 2-poly 3-metal CMOS technology. The 10bit 120M sample/s ADC achieves 0.14LSB of DNL and 0.8LSB of INL with very low power dissipation of 75mW at 2V.

Logic circuit and method for carry and sum generation and method of designing such a logic circuit

Abstract: Logic circuit for generating carry or sum bit output by combining binary inputs, includes bit level carry generate and propagate function logic receiving binary inputs and generating bit level carry generate/propagate function bits for binary inputs by respectively logically AND and OR combining respective bits of binary inputs; logic generating high output if a carry is generated out of a first group of most significant bits of binary input or if carry propagate function bits for the most significant bits are all high; logic for receiving bit level carry generate and propagate function bits for binary inputs to generate high output if any of carry generate function bits for the most significant bits are high or if carry is generated out of another group of least significant bits of binary input; and logic for generating the carry or sum bit output by combining outputs of the two logics.

Secret-key-controlled reversible circuit and corresponding method of data processing

Abstract: A combinatorial key-dependent network (46), suitable for the encryption/decryption of data on buses and in memories of data-processing devices, comprises a number of layers, where each layer is composed of a number of elementary building blocks (2) operating on very small block sizes. A generic building block (2) acts on a small number of input data bits, which are divided into two groups of m and n bits, respectively. The m input bits, which are passed to the output intact, are used to select k out of 2mk key bits by a multiplexer circuit; the k bits are then used to select an (nxn)-bit reversible transformation (Rk) acting on the remaining n input bits to produce the corresponding n output bits. The total number of the key bits in the building block is thus 2mk, which can easily be made larger that m+n. An inverse building block is the same except that the reversible transformations RK are replaced by their inverses Rk-1.