Showing papers on "Effective number of bits published in 2004"

A 70-mW 300-MHz CMOS continuous-time /spl Sigma//spl Delta/ ADC with 15-MHz bandwidth and 11 bits of resolution

Abstract: A wide-bandwidth continuous-time sigma-delta ADC is implemented in a 0.13-/spl mu/m CMOS. The circuit is targeted for wide-bandwidth applications such as video or wireless base-stations. The active blocks are composed of regular threshold voltage devices only. The fourth-order architecture uses an OpAmp-RC-based loop filter and a 4-bit internal quantizer operated at 300-MHz clock frequency. The converter achieves a dynamic range of 11 bits over a bandwidth of 15 MHz. The power dissipation is 70 mW from a 1.5-V supply.

Blind adaptive equalization of mismatch errors in a time-interleaved A/D converter system

Abstract: To significantly increase the sampling rate of an A/D converter (ADC), a time-interleaved ADC system is a good option. The drawback of a time-interleaved ADC system is that the ADCs are not exactly identical due to errors in the manufacturing process. This means that time, gain, and offset mismatch errors are introduced in the ADC system. These errors cause distortion in the sampled signal. In this paper, we present a method for estimation and compensation of the mismatch errors. The estimation method requires no knowledge about the input signal except that it should be bandlimited to the Nyquist frequency for the complete ADC system. This means that the errors can be estimated while the ADC is running. The method is also adaptive to slow changes in the mismatch errors. The estimation method has been validated with simulations and measurements from a time-interleaved ADC system.

A 1.8-V 1.6-GSample/s 8-b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency

Abstract: This study demonstrates for the first time the significant performance enhancement that calibration brings to folding-interpolating analog-to-digital converters (ADCs). The resulting 1.8-V ADC in 0.18-/spl mu/m CMOS achieves a conversion rate exceeding 1.6 GSample/s, since the amplifier device sizes can be minimized to maximize speed without the restriction of device matching. At 1.6 GS/s, the ADC achieves 0.15 LSB DNL, 0.35 LSB INL, 7.6 effective number of bits (ENOBs) at 100 MHz input, and 7.26 ENOB at Nyquist. At this speed, current consumption from a single 1.8-V supply is 245 mA analog, 185 mA digital, and 90 mA for the LVDS drivers. The ac performance is approximately 1.5 ENOBs higher compared to the same circuit with calibration disabled. The use of best design practices to optimize the ADC linearity prior to introducing calibration resulted in this small required dynamic calibration range, simplifying the calibrator circuitry and resulting in stable continuous performance over time without recalibration. Therefore, the fully on-chip calibration is performed automatically, just one time at power-up.

Methods of increasing the reliability of a flash memory

Abstract: A multi-level flash memory cell is read by comparing the cell's threshold voltage (111, 110, 101, 100, 011, 010, 001, 000) to a plurality of integral reference voltages (Vmin, V1, V2, V3, V4, V5, V6, V7, and Vmax) and to a fractional reference voltage (V0.5, V1.5, V2.5, V3.5, V4.5, V5.5, V6.5, and V7.5). Multi-level cells of a flash memory are programmed collectively with data and redundancy bits at each significance level, preferably with different numbers of data and redundancy bits at each significance level. The cells are read collectively, from lowest to highest significance level, by correcting the bits at each significance level according to the redundancy bits and adjusting the bits of the higher significance levels accordingly. The adjustment following the correction of the least significant bits is in accordance with comparisons of a cell's threshold voltages to fractional reference voltages.

Improved determination of the best fitting sine wave in ADC testing

Abstract: The sine wave test of an analog-to-digital converter (ADC) means to excite the ADC with a pure sine wave, look for the sine wave which best fits the output in least squares (LS) sense, and analyze the difference. This is described in the IEEE standards 1241-2000 and 1057-1994. Least squares is the "best" fitting method most of us can imagine, and it yields very good results indeed. Its known properties are achieved when the error (the deviation of the samples from the true sine wave) is random, white (the error samples are all independent), with zero mean Gaussian distribution. Then, the LS fit coincides with the maximum likelihood estimate of the parameters. However, in sine wave testing of ADCs, these assumptions are far from being true. The quantization error is partly deterministic, and the sample values are strongly interdependent. For sine waves covering less than, say, 20 quantum levels, this makes the sine wave fit worse than expected, and since small changes in the sine wave affect the residuals significantly, especially close to the peaks, ADC error analysis may become misleading. Processing of the residuals [e.g., the calculation of the effective number of bits, (ENOB)] can exhibit serious errors. This paper describes this phenomenon, analyzes its consequences, and suggests modified processing of samples and residuals to reduce the errors to negligible level.

A 5-b 10-GSample/s a/D converter for 10-gb/s optical receivers

Abstract: A 5-b flash A/D converter (ADC) is developed in an 0.18-/spl mu/m SiGe BiCMOS that supports sampling rates of 10 Gsample/s. The ADC is optimized to operate in digital equalizers for 10-Gb/s optical receivers, where the ADC has to deliver over three effective number of bits (ENOBs) at Nyquist. A fully differential flash ADC incorporating a wide-band track-and-hold amplifier (THA), a differential resistive ladder, an interpolation technique, and a high-speed comparator design is derived to resolve the aperture jitter and metastability error. The ADC achieves better than 4.1 effective bits for lower input frequencies and three effective bits for Nyquist input at 10 GS/s. The ADC dissipates about 3.6 W at the maximum clock rate of 10 GS/s while operating from dual -3.7/-3V supplies and occupies 3/spl times/3mm/sup 2/ of chip area.

Method and apparatus for start-up of analog-to-digital converters

Abstract: An analog-to-digital (ADC) converter circuit that converts an analog input signal into a digital output circuit includes a calibration coefficient computation circuit for computing calibration coefficients of a calibration filter. The calibration coefficient computation circuit includes a switching device adapted to switch the analog input signal delivered to the ADC circuit between on and off states, and includes a pseudo-random signal generator adapted to input a pseudo-random signal to the ADC circuit. During a start-up phase of the ADC circuit, the ADC circuit, the switching device turns off the analog input signal to the ADC circuit, the pseudo-random signal generator inputs a pseudo-random signal into the ADC circuit, and the calibration coefficient computation circuit computes the calibration coefficients of the calibration filter. This ADC circuit configuration reduces startup time for the calibration filter to only a few clock cycles.

Method and apparatus for automatic gain control of a multi-carrier signal in a communication receiver

Abstract: A receiver operates to AGC a multi-carrier signal through a corresponding number of inner loops and an outer loop AGC processes. A first number of bits for representing the multi-carrier signal with a limited amount of interference is determined through a calibration mode process. The first number of bits provides for quantization of the multi-carrier signal at an outer loop AGC to a maximum quantization level. After the received signal power estimate is reached a predetermined “ON” threshold, the outer loop AGC is operated at a second number of bits higher than the first number of bits to allow a quantization of possible interference in accordance with a difference of the first and second number of bits. The outer loop AGC switches back to use the first number of bits when the received signal power estimate falls below a predetermined “OFF” threshold.

Frame structure for an adaptive modulation wireless communication system

Abstract: A method of simplifying the encoding of a predetermined number of bits of data into frames including adding error coding bits so that a ratio of the frame length times the baud rate of the frame times he bit packing ratio of the data divided the total bits of data is always an integer. The method may also convolutionally encode the bits of data so that the same equation is also always an integer.

Flexible rate split method for MIMO transmission

Abstract: A method for transmitting a packet of N input bits includes encoding all of the N bits as a single entity, such as with an interleaver of length N within a turbo coder, outputting M encoded bits, channel interleaving the M bits, splitting the M encoded bits into a parallel first and second portion, and transmitting them over separate channels to achieve spatial diversity. The size of the first and second portion is determined based on a closed feedback loop that provides some knowledge of the channel, preferably a measure of channel capacity. The feedback loop may also provide channel knowledge to a subpacket selector associated with each transmit antenna, which determines an appropriate rate for that channel and selects subpackets to fill a transmission packet for that channel. The subpacket selectors choose a subpacket of systematic bits and fill the remaining transmission packet size with subpackets of parity bits. Eigenvectors maybe employed to transmit each transmission packet over more than one channel with a power disparity between the channels. A transmitter according to the present invention is also described.

A 21-mW 8-b 125-MSample/s ADC in 0.09-mm/sup 2/ 0.13-/spl mu/m CMOS

Abstract: This paper presents an 8-b two-step subranging analog-to-digital (ADC) using interpolation, averaging, offset compensation, and pipelining techniques to accomplish an effective number of bits of 7.6 b at 125 MSample/s. The 0.13-/spl mu/m CMOS ADC occupies 0.09 mm/sup 2/ and consumes 21 mW.

An 8b 600MS/s 200mW CMOS folding A/D converter using an amplifier preset technique

Abstract: An 8b CMOS folding ADC with resistive averaging and interpolation exhibits 7.5 ENOB and a maximum sample frequency of 600MS/s while dissipating only 200mW. The ADC utilizes preset switches at the outputs of the pre-amplifiers. Chip area is 0.2mm/sup 2/, and supply voltage is 3.3/1.8V in 0.35/0.18/spl mu/m CMOS.

An 8-bit 2-Gsample/s folding-interpolating analog-to-digital converter in SiGe technology

Abstract: This paper deals with the design and implementation of an 8-bit 2-Gsample/s folding-interpolating analog-to-digital converter (ADC) using a SiGe technology with a unity gain cutoff frequency f/sub T/ of 47 GHz. The high-speed high-resolution ADC has applications in direct IF sampling receivers for wideband communication systems. The converter occupies an area of 3.5 mm/spl times/3.5 mm including pads and exhibits an effective resolution bandwidth of 700 MHz at a sampling rate of 2 Gsample/s. The maximum DNL and INL are 0.5 and 1 LSB, respectively. The ADC dissipates 3.5W (including output buffers) from a 3.3-V power supply.

Effective number of resolution bits in direct sensor-to-microcontroller interfaces

Abstract: Microcontrollers with embedded timers can directly measure resistive and capacitive sensors by determining the charging or discharging time of an RC circuit that includes the sensor. This time-to-digital conversion is affected by the quantization of the timer and the trigger noise, which limit the resolution to an effective number of bits (ENOB). This paper analyses the standard uncertainty and the ENOB of that time-to-digital conversion. When interfacing resistive sensors and the capacitor C is small, quantization effects predominate over trigger noise effects, and ENOB increases for increasing C. But, for capacitor values larger than a given C, trigger noise effects predominate and the ENOB remains constant regardless of C. Therefore, an optimal time constant yields the best speed–ENOB trade-off. This type of sensor interface was implemented by using an AVR microcontroller with an embedded 16-bit timer connected to a resistor simulating a Pt1000-type temperature sensor. The experimental results agree with the theoretical predictions. If the time was determined from a single observation, the optimal time constant was about 2–3 ms and the ENOB was about 11.5 b, which corresponds to a 0.22 Ω resolution. By averaging ten observations, that resolution improved to 13.5 b (0.05 Ω).

Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0.13/spl mu/m CMOS

Abstract: This work presents a 6-bit fully-differential current steering digital-to-analog converter (DAC), oversampled and 2/sup nd/ order noiseshaped. It is implemented in a 0.13 /spl mu/m standard CMOS process, using only regular threshold voltage devices. The circuit is targeted at ADSL2+ central-office (CO) applications. Clocked at 105 MHz from a low-jitter PLL, it yields a multi-tone power ratio (MTPR) higher than 75 dBc for DMT signals, with an output swing of 1.4 V peak-to-peak. It has an effective resolution of more than 14.5 ENOBs (effective number of bits), consuming only 9 mW from a single 1.5 V supply.

Method for reducing DAC resolution in multi-bit sigma delta analog-to digital converter (ADC)

Abstract: A method for reducing the resolution of a digital-to-analog converter in a multi-bit sigma-delta ADC is described. With the addition of digital sigma-delta modulators in the feedback path of a sigma-delta ADC, the truncation errors between the digital word output of the multi-bit sigma-delta ADC to the DAC input can be shaped to higher order than that of the quantization error. Thus, the DAC resolution can be reduced and the implementation of DEM for multi-bit DAC can be avoided. A preferred embodiment comprises selecting an outermost feedback loop in a sigma-delta ADC that has not been replaced and replacing it with a circuit with an equivalent transfer function. The circuit can be further enhanced with an additional term if the order of the noise shaping of the circuit is less than the order of the noise shaping of the sigma-delta ADC.

SAR ADC providing digital codes with high accuracy and high throughput performance

Abstract: An aspect of the invention improves accuracy of digital codes generated at the output of a SAR ADC by using multiple reference voltages. A first reference voltage is used to generate an equivalent voltage corresponding to previous resolved bits and a second reference voltage is used to generate equivalent voltage corresponding to the bits being presently resolved. Another aspect of the present invention provides an ADC with high SNR as well as high throughput performance. Such a feature may be achieved by resolving some of the MSBs of the digital code using a high speed and low SNR DAC and remaining bits of the digital code using a high SNR DAC.

Image display device supplied with digital signal and image display method

Abstract: A current supply circuit includes a bit select circuit selectively providing even-numbered bits or odd-numbered bits of eight bit image data, and supplies a gray-scale current corresponding to the bits provided from the bit select circuit to a pixel In a one-frame period, a time length for supplying a current corresponding to the even-numbered bits to the light-emitting element is set twice as large as a time length for supplying a current corresponding to the odd-numbered bits By setting 16 levels of the gray-scale current for four bits, a current-time product of a current passing through the light-emitting element during the one-frame period can be controlled to 256 levels for eight bits Thereby, an image display device provided at each of the pixels with the light-emitting element can reduce sizes of circuits generating the gray-scale current in accordance with a digital signal

Minimized SAR-type column-wide ADC for image sensors

Abstract: An improved analog-to-digital converter wherein a minimal amount of circuitry is provided for conversion of an analog signal to a series of digital bits. A comparator is provided for generating digital values to which the digital bits correspond. A digital-to-analog converter is provided for generating, via successive approximation, a feedback analog signal based on bits previously generated by the comparator. The analog-to-digital converter compares the feedback analog signal to the input analog signal, and based on the comparison generates a digital value that corresponds to a digital bit. In the method of the invention, an analog signal is converted to a digital value using the analog-to-digital converter, and a digital-to-analog converter comprising two capacitors and a reference selector generates, via successive approximation, a feedback analog signal that is applied to a comparator for comparison to the input analog signal being digitized.

Half-rate vocoder

Abstract: Encoding a sequence of digital speech samples into a bit stream includes dividing the digital speech samples into one or more frames, computing model parameters for a frame, and quantizing the model parameters to produce pitch bits conveying pitch information, voicing bits conveying voicing information, and gain bits conveying signal level information. One or more of the pitch bits are combined with one or more of the voicing bits and one or more of the gain bits to create a first parameter codeword that is encoded with an error control code to produce a first FEC codeword that is included in a bit stream for the frame. The process may be reversed to decode the bit stream.

A criterion for optimizing bit-reduced post-correction of AD converters

Abstract: Dynamic digital post-correction of analog-to-digital converters (ADCs) is considered. A generalized dynamic correction method is proposed and a framework for analyzing the related bit allocation problem is derived. Finally, this framework is employed in an optimization problem. The solution to the problem indicates which ADC output bits to use in order to maximize the signal-to-noise and distortion ratio in a post-correction system with a constraint on memory size. The proposed methods are accompanied by exemplary results obtained using experimental ADC data.

Modulation in a mobile telecommunications system

Abstract: A method of communication of data in a mobile telecommunications network involves at a transmitter first grouping the data into a first sequence of bits and a second sequence of bits. There is then a step of modulating a signal with the bits of the first sequence so that the bits of the first sequence have a first level of communication error protection provided by the modulation and with the bits of the second sequence so that the bits of the second sequence have a second level of communication error protection provided by the modulation less than the first level of communication error protection. The signal is then transmitted. At a receiver, estimates of the bits of the first sequence from the signal are detected and contributions to the signal corresponding to the estimates are determined and cancelled from the signal so as to produce a modified signal. Estimates of the bits of the second sequence are then detected from the modified signal.

A 12.5 Gsample/s optical digital-to-analog converter with 3.8 effective bits

Abstract: Optical techniques have the potential to overcome speed limitations: for digital-to-analog conversion. In this paper, we present a novel scheme for an optical digital-to-analog converter based on the coherent summation of optical phase-modulated signals. A first demonstration using commercial discrete components yielded in a 12.5 Gsample digital-to-analog converter with a nominal resolution of 6 bits and an effective number of bits (ENOB) of 3.8.

Processing of images using a limited number of bits

Abstract: The invention relates to a method as well as a system, a device, an encoder and a decoder, and a computer software product for image processing by the method. In the invention, the number of bits is limited in the bit string of a pixel to be processed, wherein the pixel is encoded with the limited number of bits. In the method, a prediction value corresponding to said pixel is searched for. If it is found, the difference between the pixel and the prediction value is determined, to select the method for encoding the bit string of said pixel. Also, a code word is encoded in the bit string, to indicate the selected encoding method. If the predicThe invention relates to a method as well as a system, a device, an encoder and a decoder, and a computer software product for image processing by the method. In the invention, the number of bits is limited in the bit string of a pixel to be processed, wherein the pixel is encoded with the limited number of bits. In the method, a prediction value corresponding to said pixel is searched for. If it is found, the difference between the pixel and the prediction value is determined, to select the method for encoding the bit string of said pixel. Also, a code word is encoded in the bit string, to indicate the selected encoding method. If the prediction value is missing, the number of bits in said pixel is limited by quantizing. By means of the invention, a fixed number of bits is obtained for all encoded pixels in an image.

Pipeline ADC digital dithering for increased digital calibration resolution

Abstract: An pipeline analog-to-digital converter (ADC) is provided that is capable of applying calibration at a resolution greater than the resolution of a digital output signal provided by the ADC. The ADC includes a calibration component adapted to apply calibration bits to digital output bits generated by stages of the pipeline and corresponding to samples of an analog input signal. The ADC also includes a random number generator that provides at least one random bit having a sub-LSB bit weight. The calibration bits and the at least one random bit are applied as a dither to the digital output bits such that, on average, the digital output signal provided by the ADC is calibrated at a sub-LSB resolution.

A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 /spl mu/m CMOS [ADC applications]

Abstract: A 1.6 GS/s track and hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR for a 950 MHz full scale input signal is 50 dB. Phase alignment is better than 2 ps and aperture uncertainty is less than 0.8 ps (RMS). The chip includes two analog to digital converters and a switching matrix to accommodate measurement of all sampled output signals and their timing relation. Chip area is 0.14 mm/sup 2/, excluding the AD converters. The chip is made in a 0.12 /spl mu/m, 1.2 V CMOS process. Power consumption of the interleaving T/H circuit is 32 mW.

Compressing signals using serially-concatenated accumulate codes

Abstract: A method compresses a set of correlated signals by first converting each signal to a sequence of integers, which are further organized as a set of bit-planes. This can be done by signal transformation and quantization. An inverse accumulator is applied to each bit-plane to produce a bit-plane of shifted bits, which are permuted according to a predetermined permutation to produce bit-planes of permuted bits. Each bit-plane of permuted bits is partitioned into a set of blocks of bits. Syndrome bits are generated for each block of bits according to a rate-adaptive base code. Subsequently, the syndrome bits can be decompressed in a decoder to recover the original correlated signals. For each bit-plane of the corresponding signal, a bit probability estimate is generated. Then, the bit-plane is reconstructed using the syndrome bits and the bit probability estimate. The sequence of integers corresponding to all of the bit-planes can then be reconstructed from the bit probability estimates, and the original signal can be recovered from the sequences of integers using an inverse quantization and inverse transform.

Noncoherent spectral analysis of ADC using filter Bank

Abstract: The aim of this paper is to propose a new spectral analysis method for an on-chip analog-to-digital converter (ADC) dynamic test. ADC characterization by spectral analysis has traditionally been done with discrete Fourier transform. This method imposes restrictions to optimize results; one of these is coherent sampling. Recently, some filter structures have been used for spectral analysis of a sinusoidal signal corrupted by harmonics and noise. In this paper, we present a new filter bank structure used for decomposing a signal into its main spectral components. The main application examined is ADC spectral parameter estimation, like signal-to-noise and distortion ratio, signal to noise ratio, total harmonic distortion, and so on, in noncoherent sampling. Computer simulations are used to demonstrate the performance of the proposed filter bank scheme. This structure is a promising built-in self-test (BIST) approach for ADC ICs.

Analog-to-Digital Converter Having Parametric Configuirablity

Abstract: A reconfigurable ADC includes a plurality of reconfigurable blocks for allowing the ADC to provide a plurality of architectures. In one embodiment, the ADC can be configured to operate in a pipeline mode and a sigma-delta mode. This arrangement provides an ADC having a relatively large range of bandwidth and resolution.