Showing papers on "Effective number of bits published in 2008"

A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator

Abstract: The ADC-SAR is fabricated in a 0.18mum 2P5M CMOS process. This SAR-ADC converter achieves 56fJ/conversion-step FOM with 58dB SNDR. It uses a comparator, named time-domain comparator, that instead of operating in the voltage domain, transforms the input and the reference voltages into pulses and compares their duration.

An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS

Abstract: Current trends in analog/mixed-signal design for battery-powered devices demand the adoption of cheap and power-efficient ADCs. SAR architectures have been recently demonstrated as able to achieve high power efficiency in the moderate-resolution/medium- bandwidth range in Craninckx, J. and Van der Plas, G., (2007). However, when the comparator determines in first instance the overall performance, as in most SAR ADCs, comparator thermal noise can limit the maximum achievable resolution. More than 1 and 2 ENOB reductions are observed in Craninckx, J. and Van der Plas, G., (2007) and Kuttner, F., (2002), respectively, because of thermal noise, and degradations could be even worse with scaled supply voltages and the extensive use of dynamic regenerative latches without pre-amplification. Unlike mismatch, random noise cannot be compensated by calibration and would finally demand a quadratic increase in power consumption unless alternative circuit techniques are devised.

A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS

Abstract: A time-interleaved ADC is presented with 16 channels, each consisting of a track-and-hold (T&H) and two successive approximation (SA) ADCs in a pipeline configuration to combine a high sample rate with good power efficiency. The single-sided overrange architecture achieves a 25% higher power efficiency of the SA-ADC compared with the conventional overrange architecture, and look-ahead logic is used to minimize logic delay in the SA-ADC. For the T&H, three techniques are presented enabling a high bandwidth and linearity and good timing alignment. Single channel performance of the ADC is 6.9 ENOB at an input frequency of 4 GHz. Multichannel performance is 7.7 ENOB at 1.35 GS/s with an ERBW of 1 GHz. The FoM of the complete ADC including T&H is 0.6 pJ per conversion step. An improved version is presented as well and achieves an SNDR of 8.6 ENOB for low sample rates, and, with increased supply voltage, it reaches a sample rate of 1.8 GS/s with 7.9 ENOB at low input frequencies and an ERBW of 1 GHz. At fin = 3.6 GHz, the SNDR is still 6.5 ENOB, and total timing error including jitter is 0.4 ps rms.

An Over-60 dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp With Only 30 dB Loop Gain

Abstract: Correlated level shifting (CLS) is introduced as a new switched-capacitor technique to provide true rail-to-rail performance while reducing errors from finite opamp gain. There is negligible kT/C noise increase and in many cases a speed advantage compared to using a high gain opamp. The gain enhancement is quantified with formulas and the general technique is compared to correlated double sampling (CDS). Results are presented from a 0.18 mum CMOS testchip of a 20 MHz, 12-bit pipelined A/D converter using CLS to reduce errors from finite opamp dc gain and limited opamp swing. It achieves 10.5 ENOB operating beyond the supply rails using an opamp circuit with 30 dB loop gain and 0.9 V supply.

Photonic subsampling analog-to-digital conversion of microwave signals at 40-GHz with higher than 7-ENOB resolution

Abstract: Conversion of analog signals into digital signals is one of the most important functionalities in modern signal processing systems. As the signal frequency increases beyond 10 GHz, the timing jitter from electronic clocks, currently limited at ~100 fs, compromises the achievable resolution of analog-to-digital converters (ADCs). Owing to their ultralow timing jitter, the use of optical pulse trains from passively mode-locked lasers has been considered to be a promising way for sampling electronic signals. In this paper, based on sub-10 fs jitter optical sampling pulse trains, we demonstrate a photonic subsampling ADC that downconverts and digitizes a narrowband microwave signal at 40 GHz carrier frequency with higher than 7 effective-number-of-bit (ENOB) resolution.

A 24GS/s 6b ADC in 90nm CMOS

Abstract: This paper presents a 24 GS/s 6 b ADC in 90 nm CMOS with the highest ENOB up to 12 GHz input frequency and lowest power consumption of 1.2 W compared to ADCs with similar performance. It uses an interleaved architecture of SAR type self-calibrating converters operating from 1 V supply combined with an array of 2.5 V T/Hs with delay, gain and offset-calibration capability.

Chopper-stabilized analog-to-digital converter

Abstract: This disclosure describes a chopper-stabilized sigma-delta analog-to-digital converter (ADC). The ADC is configured to provide accurate output at low frequency with relatively low power. The chopper-stabilized ADC substantially reduces or eliminates noise and offset from an output signal produced by the mixer amplifier. Dynamic limitations, i.e., glitching that result from chopper stabilization at low power are substantially eliminated or reduced through a combination of chopping at low impedance nodes within the mixer amplifier and feedback. The signal path of the ADC operates as a continuous time system, providing minimal aliasing of noise or external signals entering the signal pathway at the chop frequency or its harmonics. In this manner, the chopper-stabilized ADC can be used in a low power system, such as an implantable medical device (IMD), to provide a stable, low-noise output signal.

A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC

Abstract: A low-power 14-b 100-MS/s analog-to-digital converter (ADC) is described. The prototype ADC achieves low-power consumption and small die area by sharing an opamp between two successive pipeline stages. Further reduction of power and area is achieved by completely merging the front-end sample-and-hold amplifier (SHA) into the first multiplying digital-to-analog converter (MDAC) using the proposed opamp and capacitor sharing technique. The ADC, implemented in a 0.18-mum dual-gate-oxide (DGO) CMOS technology, achieves 72.4-dB signal-to-noise and distortion ratio, 88.5-dB spurious free dynamic range, and 11.7 effective number of bits at full sampling rate with a 46-MHz input while consuming 230-mW from a 3-V supply.

Time-warp correction and calibration in photonic time-stretch analog-to-digital converter

Abstract: We show how time warps caused by nonuniform wavelength-to-time mapping in the photonic time-stretch analog-to-digital converter (ADC) can be digitally measured and removed. This is combined with digital correction of wavelength-dependent Mach-Zehnder modulator (MZM) bias offset to attain a 10 GHz bandwidth digitizer with >7 effective bits of resolution and 52 dB spur-free dynamic range. To the best of our knowledge, this is the highest resolution ADC in 10 GHz bandwidth range, with at least 1 order of magnitude higher signal-to-noise ratio than ever achieved. We also demonstrate concatenation of 30 wavelength interleaved time segments with high fidelity on the path to achieving continuous time operation.

A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications

Abstract: This paper describes a 10-bit 30-MS/s subsampling pipelined analog-to-digital converter (ADC) that is implemented in a 0.18 mum CMOS process. The ADC adopts a power efficient amplifier sharing architecture in which additional switches are introduced to reduce the crosstalk between the two opamp-sharing successive stages. A new configuration is used in the first stage of the ADC to avoid using a dedicated sample-and-hold amplifier (SHA) circuit at the input and to avoid the matching requirement between the first multiplying digital-to-analog converter (MDAC) and flash input signal paths. A symmetrical gate-bootstrapping switch is used as the bottom-sampling switch in the first stage to enhance the sampling linearity. The measured differential and integral nonlinearities of the prototype are less than 0.57 least significant bit (LSB) and 0.8 LSB, respectively, at full sampling rate. The ADC exhibits higher than 9.1 effective number of bits (ENOB) for input frequencies up to 30 MHz, which is the twofold Nyquist rate (fs/2), at 30 MS/s. The ADC consumes 21.6 mW from a 1.8-V power supply and occupies 0.7 mm2, which also includes the bandgap and buffer amplifiers. The figure-of-merit (FOM) of this ADC is 0.26 pJ/step.

Analog-to-Digital Conversion in the Early Twenty-First Century

Abstract: Analog-to-digital converters (ADCs) continue to be important components of signal-processing systems, such as those for mobile communications, software radio, radar, satellite communications, and others. This article revisits the state-of-the-art of ADCs and includes recent data on experimental converters and commercially available parts. Converter performances have improved significantly since previous surveys were published (1999–2005). Specifically, aperture uncertainty (jitter) and power dissipation have both decreased substantially during the early 2000s. The lowest jitter value has fallen from approximately 1 picosecond in 1999 to < 100 femtoseconds for the very best of current ADCs. In addition, the lowest values for the IEEE Figure of Merit (which is proportional to the product of jitter and power dissipation) have also decreased by an order of magnitude. For converters that operate at multi-GSPS rates, the speed of the fastest ADC IC device technologies e.g., InP, GaAs, is the main limitation to performance; as measured by device transit-time frequency, fT, has roughly tripled since 1999. ADC architectures used in high-performance broadband circuits include pipelined (successive approximation, multistage flash) and parallel (time-interleaved, filter-bank) with the former leading to lower power operation and the latter being applied to high-sample rate converters. Bandpass ADCs based on delta-sigma modulation are being applied to narrow band applications with ever increasing center frequencies. CMOS has become a mainstream ADC IC technology because (1) it enables designs with low power dissipation and (2) it allows for significant amounts of digital signal-processing to be included on-chip. DSP enables correction of conversion errors, improved channel matching in parallel structures, and provides filtering required for delta-sigma converters. Finally, a performance projection based on a trend in aperture jitter predicts 25 fs in approximately 10 years, which would imply performance of 12 ENOB at nearly 1-GHz bandwidth. Keywords: analog-to-digital converters; signal-to-noise ratio; aperture jitter; input-referred noise; comparator ambiguity; spurious-free dynamic range; digital-signal-processing

A Time-Based Bandpass ADC Using Time-Interleaved Voltage-Controlled Oscillators

Abstract: In this paper, a bandpass analog-to-digital converter (ADC) based on time-interleaved oversampled ADC is introduced. Unlike previous delta-sigma bandpass ADCs that require accurate digital-to-analog converters and high-speed analog circuits, the proposed architecture provides bandpass function by time-interleaving first-order voltage-controlled-oscillator (VCO)-based ADCs. The use of VCO-based ADC has the advantage that its resolution is determined by the time resolution rather than the voltage resolution, thus making it attractive for future low-voltage CMOS processes. The performance of the proposed ADC is theoretically analyzed and simulated in ideal condition, as well as in nonideal condition, in the presence of nonlinearity, sampling clock jitter, and mismatch.

A Background Sample-Time Error Calibration Technique Using Random Data for Wide-Band High-Resolution Time-Interleaved ADCs

Abstract: Sample-time error among the channels of a time-interleaved analog-to-digital converter (ADC) is the main reason for significant degradation of the effective resolution of the high-speed time-interleaved ADC. A calibration technique for sample-time mismatches has been proposed and implemented at a low level of complexity. The calibration method uses random data and is especially suitable for ADCs used in digital data communication systems. An 800-MS/s four-channel, time-interleaved ADC system has been implemented to evaluate the performance of the technique. The experimental results show that the spurious-free dynamic range of the ADC system is improved to 58.1 dB at 350 MHz. The ADC system achieves a signal-to-noise and distortion ratio of 59.6 dB at 5 MHz and 50.1 dB at 350 MHz after calibration.

A 1-V 1.25-GS/S 8-Bit Self-Calibrated Flash ADC in 90-nm Digital CMOS

Abstract: We present an 8-bit 1.25-GS/s flash analog-to-digital converter (ADC) in 90-nm digital CMOS with wide analog input bandwidth and low power dissipation. The ADC employs two key techniques: a self-biased track-and-hold amplifier which enhances the ADC full-scale voltage and enables the converter operating under a single 1-V supply; and an improved calibration scheme based on reference pre-distortion to enhance the ADC linearity without sacrificing its sampling speed. The prototype converter thus achieves 7-, 6.9-, 6.5-bit ENOB at 1.25 GS/s for input signal frequencies of 10 MHz, 600 MHz, and 1.3 GHz, respectively, and better than 52-dB SFDR across the full Nyquist-band, while dissipating 207 mW from a single 1-V supply.

A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS

Abstract: A 10.3 GS/s ADC with 5 GHz input BW and 6 bit resolution in 90 nm CMOS is presented. The architecture is based on an 8 way interleaved/ pipelined ADC using open-loop amplifiers and digital calibration. The measured performance is 5.8 ENOB (36.6 dB SNDR) for a 100 MHz input signal and 5.1 ENOB (32.4 dB SNDR) for a 5 GHz input (Nyquist) with phase offset correction across the interleaved array.

A process-scalable low-power charge-domain 13-bit pipeline ADC

Abstract: A 13-bit ADC is implemented using a novel charge-domain architecture. Enhanced bucket-brigade circuitry and a tapered charge pipeline provide precision charge-domain operation in a standard CMOS process, while eliminating the need for signal-path op-amps. The prototype ADC, implemented in 0.18 mum CMOS, provides 10.65 ENOB at 250 MS/s while consuming only 140 mW, yielding an exceptionally low FoM of 0.28 pJ/conversion-step. Simulations indicate that the architecture and circuitry are well suited to scaling below 90 nm.

A Histogram-Based Testing Method for Estimating A/D Converter Performance

Abstract: A sine-wave histogram-testing structure for analog-to-digital converters (ADCs) is proposed. The ADC static parameters, i.e., offset error, gain error, and nonlinearity errors, are directly obtained from the sine-wave histogram test. Then, the obtained static parameters are related to the estimation of the degraded signal-to-noise ratio (SNR) value. Therefore, the relationships among these parameters are analyzed, and a single sine-wave histogram test can be performed to evaluate the ADC. With the appropriate approximations in the reference sine-wave histograms and the estimations of the ADC parameters, the realization of an ADC output analyzer circuit could be a simple task. An ADC output analyzer circuit is therefore developed and synthesized using a 0.18-mum technique to analyze the outputs of an 8-bit ADC and estimate its performances using the proposed method.

A 6-bit 5-GSample/s Nyquist A/D converter in 65nm CMOS

Abstract: A 6-bit Nyquist A/D converter (ADC) that converts at 5 GHz is reported. Using a wideband track-and-hold amplifier, array averaging, reset switches on analog signal paths, and phase-adjusted clocking for cascaded comparators, a 6-bit flash ADC achieves better than 5 effective bits for input frequencies up to 2.5 GHz at 5 GSample/s. This ADC does not rely on time interleaving, digital calibration, and post data processing for its dynamic performance. Peak INL and DNL are less than 0.7 LSB and 0.6 LSB, respectively. This ADC consumes about 320 mW from 1.3 V at 5 GSample/s. The chip occupies 0.3 mm2 active area, fabricated in 65 nm CMOS.

Error correction coding techniques for non-volatile memory

Abstract: During programming of memory cells, calculating sigma bits for cells programmed at each program level based on attributes of the cells, such an index representing a cell's bit location in the memory array. For example, summing the indexes with an increasing weight factor, such as factor-of-2. During read, new sigma bits are calculated and compared with the stored sigma bits. A difference between the new sigma bits and the stored sigma bits may define a unique combination of indexes, enabling searching for, finding and correcting the read errors. The sigma bits may be used to correctly identify which cells were programmed at which program level, despite threshold voltage drift and/or overlap. Programming may be performed with advertent overlapping distributions, and the bits can be sorted out.

Transformer-isolated analog-to-digital converter (ADC) feedback apparatus and method

Abstract: A transformer-isolated analog-to-digital converter (ADC) feedback apparatus and method provides reduction of circuit complexity in high power/high voltage systems having a transformer-isolated sensing circuit. The feedback apparatus is a circuit including an ADC for receiving an analog input signal and a transformer having a first winding that receives a modulated output of the analog-to-digital converter. A second winding of the transformer provides an isolated data output of the ADC. A demodulator is coupled to the second winding of the transformer and demodulates the isolated output to generate a digital representation of the analog input signal. The ADC may be a delta-sigma converter and the demodulator may be the corresponding decimation filter. The circuit further includes an isolation circuit for introducing a clock signal and/or power supply waveform at the second winding of the transformer, so that the ADC circuit is supplied with an isolated clock and/or an isolated power supply.

Balanced data bus inversion

Abstract: A method and apparatus for balancing an output load using data bus inversion is disclosed. In brief, one such technique comprises measuring the “balance” of data bits across a data bus (e.g., the number of zero values compared to the number of one values in a set of parallel data bits). If the data bits are unbalanced by a specified amount, a portion of the bits on the data bus are inverted, and the data bits, including the inverted portion, are transmitted. Also, a data bus inversion bit is set to a particular value and transmitted with the data bits to indicate that data bus inversion was used. If the data signal is not unbalanced (i.e., the bits on the data bus do not comprise an unbalanced number of logic values), then the bits on the data bus are transmitted as they are detected, and the data bus inversion bit is set to another particular value to indicate that data bus inversion was not used.

A 6b stochastic flash analog-to-digital converter without calibration or reference ladder

Abstract: A 6-bit stochastic flash ADC is presented. By connecting many comparators in parallel, a reference ladder is avoided by allowing random offset to set individual trip points. The ADC transfer function is the cumulative density function of comparator offset. A technique is proposed to improve transfer function linearity by 8.5 dB. A test chip, fabricated in 0.18 mum CMOS, achieves ENOB over 4.9 b up to 18 MS/s with 900 mV supply and comparator offset standard deviation of 140 mV Comparators are digital cells to allow automated synthesis. Total core power consumption when fs = 8 MHz is 631muW.

A 0.6-to-1V inverter-based 5-bit flash ADC in 90nm digital CMOS

Abstract: A 0.6-to-1 V inverter-based 5-bit flash ADC in 90 nm digital CMOS is presented. Single-ended comparators are formed using digital inverters and resistors. The comparators are designed for compatibility with nanoscale CMOS lithography. A single-ended flash architecture was used without a front-end sample-and-hold. The ADC achieves a low frequency effective number of bits (ENOB) between 4.08 bits and 4.45 bits without calibration. Voltage scaling is demonstrated by 60 MS/s, 300 MS/s, and 600 MS/s operation at 0.6 V, 0.8 V, and 1 V, respectively. Power scales from 1.3 mW to 6.7 mW.

Apparatus and method for successive approximation analog-to-digital conversion

Abstract: A successive approximation analog-to-digital converter (ADC) includes a binary-weighted capacitor array, quantizer, and control block. One end of each capacitor is connected to the input of the quantizer, and a second end of each capacitor is controlled by the control block through a driver. A voltage is sampled, quantized, and stored as the most significant bit of the ADC's output. Depending on the result of the quantization, the control block toggles the driver of one of the capacitors corresponding to the most significant bit. The voltage at the common node is sampled again to obtain a second bit of the ADC's output. The operations are repeated as needed to obtain and store additional bits of the ADC's output. Similar configuration and process are described for a differential ADC. The operation is asynchronous, allowing extra time for metastable states only when such states occur.

Computationally efficient convolutional coding with rate-matching

Abstract: An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate

GMSK-receiver with interference cancellation

Abstract: A GMSK receiver with interference cancellation includes a linear equalizer (309) configured to be coupled to a received signal from a first antenna and to provide first soft bits, an adaptive estimator, e.g., adaptive MLSE (315) coupled to the first soft bits and configured to provide second soft bits; a quality assessor coupled to the first soft bits and configured to provide a quality indication; and a switching function (325) coupled to the linear equalizer and the adaptive MLSE and controlled in accordance with the quality indication to provide output soft bits (331) corresponding to at least one of the first soft bits and the second soft bits. The GMSK receiver can be extended to multiple antennas and corresponding methods for interference cancellation in a GMSK signal are discussed.

A novel flash analog-to-digital converter

Abstract: this paper a new ADC architecture of flash type is proposed. This proposed N-bit flash ADC replaces the (2N-1)-to- N encoder with two (2N/2 -1)-to-(N/2) encoders to accomplish the encoding of the least significant bits and the most significant bits respectively. A 6-bit ADC of this architecture is implemented. The physical circuit is more compact than the existing ones. Power, processing time and area cost are all minimized. In addition, a new encoding algorithm is proposed to enhance the bubble error tolerance of an ADC. The encoders that have the capability of removing the bubble errors always suffer the problem of long latency. It becomes a bottleneck in the design of high speed flash ADC nowadays. In the proposed 6-bit ADC, the trade-off between bubble tolerance and latency is optimized by applying the proposed encoding algorithm into the encoder circuit design. Delay of 3 gate-levels or fewer is required for processing the encoding and the maximum error induced bubble is 7 LSB. Simulation results demonstrate the benefits introduced above. This new flash ADC offers an excellent choice for modern high speed ADC application.

Several approaches to ADC transfer function approximation and their application for ADC non-linearity correction

Abstract: The performance of current electronic devices is mostly limited by analog front-end and analog-to-digital converter’s (ADC) actual parameters. One of the most important parameters is ADC nonlinearity. The correction of this imperfection can be accomplished in the output data but only if the nonlinearity is well characterized. Many approaches to ADC characterization have been proposed in scientific articles in the last several years. In this paper three different approximations of ADC low-frequency non-linearity (common polynomials, Chebyshev polynomials and Fourier series) were analyzed and the practical applicability, approximation accuracy and noise sensitivity were investigated. The first results of nonlinearity correction were presented, too.

FPGA Implementation of SQUASH

Abstract: Passive RFID tags are devices with very poor computational capability. How- ever an increasing number of applications require authentication of the tag. For this purpose, a simple solution is to use a challenge-response protocol. For exam- ple, the reader can send a random challenge R and the tag responds H(R + S), where S is a secret known by the reader and H is a hash function. Then, the reader can check whether the tag knows S. SQUASH, introduced by Adi Shamir in February 2008 [1], is a new hash function designed for this task. In this ar- ticle, we describe an FPGA implementation of this algorithm minimizing the resources. SQUASH is based on the one-way function c = m2 mod n coming from the Rabin cryptosystem [2]. To make it secure, the binary length of n must be at least 1000 bits long [8]. In [1], the author suggests using a 64-bit non-linear feedback shift register to generate m, a not yet factorized Mersenne's number (2x - 1) as modulus n, and to send out the bits of c without storing them. This process avoids storing three 1000-bit long numbers. The multiplications are achieved by on-the- y convolutions, sending each bit as soon as it is computed. Consequently, the only needed memory aims at storing the carry of the previous steps in the convolution. For the output, a window of 32 or 64 (or more) bits in c is used. It yields a hash function with inputs of 64 bits that is scalable in output. In this paper, we propose implementations designed in order to minimize the resources, possibly at the cost of an increased execution time. The target device is a Xilinx Virtex-4 XC4VLX200-10 FPGA. The algorithm recommended by Adi Shamir has 64 bits in input and 32 in output, and n = 21277 - 1. To reduce the hardware cost, we minimized the number of registers in the implementation data and control part. On the XC4VLX200, the design results require 377 slices. The full execution time to produce 32 bits is 63,250 clock cycles at 222 MHz, so we reach a throughput of 112,300 bits per second. We also implemented the algorithm with other size numbers. For 128 bits in input and 64 in output, we get 619 slices and 104,114 clock cycles at 206 MHz. In general, the length of the output in uences the execution time while the length of the input in uences the number of registers and slices.