Showing papers on "Effective number of bits published in 2010"

Channel Estimation with Low-Precision Analog-to-Digital Conversion

Abstract: We consider the problem of estimating the impulse response of a dispersive channel when the channel output is sampled using a low-precision analog-to-digital converter (ADC). While traditional channel estimation techniques require about 6 bits of ADC precision to approach full-precision performance, we are motivated by applications to multiGigabit communication, where we may be forced to use much lower precision (e.g., 1-3 bits) due to considerations of cost, power, and technological feasibility. We show that, even with such low ADC precision, it is possible to attain near full-precision performance using closed-loop estimation, where the ADC input is dithered and scaled. The dither signal is obtained using linear feedback based on the Minimum Mean Squared Error (MMSE) criterion. The dither feedback coefficients and the scaling gains are computed offline using Monte Carlo simulations based on a statistical model for the channel taps, and are found to work well over wide range of channel variations.

A Low-Power Capacitive Charge Pump Based Pipelined ADC

Abstract: A low-power pipelined ADC topology is presented which uses capacitive charge pumps, source-followers, and digital calibration to eliminate the need for power-hungry opamps to achieve good linearity in a pipelined ADC. The differential charge pump technique achieves >10-bit linearity, and does not require an explicit common-mode-feedback circuit. The ADC was designed to operate at 50 MS/s in a 1.8 V, 0.18 ?m CMOS process, where measured results show the peak SNDR and SFDR of the ADC to be 58.2 dB (9.4 ENOB), and 66 dB respectively. The ADC consumes 3.9 mW for all active circuitry and 6 mW for all clocking and digital circuits.

A 12b 50MS/s 3.5mW SAR assisted 2-stage pipeline ADC

Abstract: A 12b 50MS/s ADC is presented that pipelines a first stage 6b MDAC with a second stage 7b SAR ADC. The first stage uses a low-power SAR architecture for the sub-ADC, to achieve the large 6b stage resolution. A “half-gain” MDAC reduces the output swing and increases the closed-loop bandwidth of the op-amp in the first stage. This ADC consumes 3.5mW from a 1.3V supply, achieves an ENOB of 10.4b at Nyquist, and an FOM of 52fJ/conversion-step.

A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique

Abstract: A 9-bit 80 MS/s successive approximation register analog-to-digital converter (ADC), which is suitable for low power and a small area, is presented. The 9-bit capacitor array consists of only 16 unit capacitors and a coupling capacitor due to the proposed binary-weighted split-capacitor arrays with a merged-capacitor switching technique. The proposed ADC includes a comparator with offset cancellation and uses digital calibration for error correction. The ADC is implemented in a 65-nm complimentary metal-oxide-semiconductor technology and occupies an active area of 0.068 mm2 with a reference buffer. The differential and integral nonlinearities of the ADC are less than 0.37 and 0.40 LSB, respectively. The ADC shows a signal-to-noise-distortion ratio of 50.71 dB, a spurious-free dynamic range of 66.72 dB, and an effective number of bits of 8.13 bits with a 78 MHz sinusoidal input at 80 MS/s. The ADC consumes 3.4 mW with the reference buffer at a 1.0-V supply and achieves a figure of merit of 78 fJ/conversion step.

A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS

Abstract: This paper reports a subranged SAR ADC consisting of a 3.5-bit flash coarse ADC, a 6-bit SAR fine ADC, and a differential segmented capacitive DAC. The flash ADC controls thermometer MSBs of the DAC and SAR ADC controls the binary LSBs. The segmented DAC improves DNL during MSB transitions. The merged switching of MSB capacitors enhances operation speed. The 9-bit 150-MS/s ADC consumes 1.53 mW from a 1.2-V supply. The ENOB is 8.69 bit and ERBW is 100 MHz. The FOMs at 1.2 V, 150 MS/s and 1 V, 100 MS/s are 24.7 and 17.7 fJ/conversion-step, respectively. At 1.3-V supply voltage, the sampling rate achieves 200 MS/s.

An 18 b 12.5 MS/s ADC With 93 dB SNR

Abstract: This paper presents a precision 18-bit 12.5 MS/s ADC that was designed primarily for digital X-ray imaging systems. This ADC was intended to have a faster output data rate than the precision successive approximation ADCs normally chosen for these systems but with similar DC accuracy and dynamic range. The chosen architecture consists of a pipeline of two multi-bit successive approximation converters. The first successive approximation ADC generates an initial coarse conversion result. The DACs within this converter are then used to generate a residue which is amplified by a residue amplifier before being converted by a second successive approximation ADC. Four comparators within each ADC allow 2 bits to be determined each bit trial. Capacitor mismatch errors are digitally corrected with error coefficients stored in non-volatile memory. Dither is used to reduce the effect of errors in the flash ADC within the second ADC. The ADC was implemented on 0.25 m CMOS process with PIP capacitors and achieves a SNR of 93 dB with a 50 kHz input tone. INL and DNL are within LSB and LSB respectively. Power consumption is 105 mW, excluding LVDS interface power.

Bulk Voltage Trimming Offset Calibration for High-Speed Flash ADCs

Abstract: A bulk voltage trimming offset calibration technique is presented for flash analog-to-digital converters (ADCs). Offset calibration is achieved by digitally adjusting the bulk voltages of the preamplifier input devices. Without introducing additional capacitive loading in the analog path, this technique improves the accuracy of flash ADCs while not impairing their high-speed performance. A 4-bit ADC in 90-nm CMOS with the proposed technique achieves 3.71 effective number of bits (ENOB) at 5-GS/s sampling rate with 2.5-GHz effective resolution bandwidth (ERBW). The calibration generally improves ENOB by approximately 0.5 bit after calibration. The ADC consumes 86 mW at 5 GS/s with a 2.5-GHz input achieving a 1.32-pJ/convstep figure of merit. The ADC occupies 0.135-mm2 chip area.

An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count

Abstract: This paper reports an asynchronous binary-search analog-to-digital converter (ADC) with reference range prediction. An original N-bit binary-search ADC requires 2N - 1 comparators while the proposed one only needs 2N - 1 ones. Compared to the (high speed, high power) flash ADC and (low speed, low power) successive approximation register ADC, the proposed architecture achieves the balance between power consumption and operation speed. The proof-of-concept 5-bit prototype only consists of a passive track-and-hold circuit, a reference ladder, 9 comparators, 56 switches and 26 static logic gates. This compact ADC occupies an active area of 120 × 50 μm2 and consumes 1.97 mW from a 1-V supply. At 800 MS/s, the effective number of bits is 4.40 bit and the effective resolution bandwidth is 700 MHz. The resultant figure of merit is 116 fJ/conversion-step.

Design of a Split-CLS Pipelined ADC With Full Signal Swing Using an Accurate But Fractional Signal Swing Opamp

Abstract: Building on the technique of correlated level shifting (CLS), Split-CLS is introduced as a viable way to enable the design of high performance, high resolution A/D converters in deep submicron CMOS processes. One possible implementation of Split-CLS is presented, which achieves very high effective gain, and combines the fast, high efficiency charging of a zero-crossing based circuit (ZCBC) with the high-accuracy, low power settling of a double-cascode telescopic opamp. A dynamic zero-crossing detector (ZCD) conserves power in the ZCBC by only creating high bandwidth in the ZCD near the zero-crossing instant. Measured results are presented from a pipelined A/D converter fabricated in 0.18 m CMOS. Using the Split-CLS structure, an opamp with 300 mV output swing is used to produce a pipeline stage output swing of 1.4 V. The proof-of-concept test chip achieves 68.3 dB SNDR (11.1b ENOB) and 76.3dB SFDR while sampling at 20 MHz, and consumes 17.2 mW at 1.8 V supply.

A zero-crossing based 12b 100MS/s pipelined ADC with decision boundary gap estimation calibration

Abstract: This paper describes a 12-bit zero-crossing based pipeline 100-MS/s ADC. The prototype ADC, fabricated in a 90-nm CMOS process, occupies 0.32 mm2. The capacitor mismatch is calibrated by decision boundary gap estimate algorithm that runs in the background. It achieves an ENOB of 10.2 bits for a 49 MHz input signal and dissipates 6.2 mW from a 1.2V supply for a FOM of 53fJ/step.

A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme

Abstract: In high-speed Flash analog-to-digital converters (ADCs), preamplifiers are often placed in front of a comparator to reduce metastability errors and enhance comparison speed. The accuracy of a Flash ADC is mainly limited by the random offsets of preamplifiers and comparators. This paper presents a 5-b Flash ADC with a digital random offset calibration scheme. For calibration, programmable resistive devices are used as the loading devices of the second-stage preamplifiers. By adjusting the calibration resistors, the input-referred offset voltage of each comparator is reduced to be less than 1/2 LSB. Fabricated in a 0.13-?m CMOS process, experimental results show that the ADC consumes 120 mW from a 1.2-V supply and occupies a 0.18- mm2 active area. After calibration, the peak differential non-linearity (DNL) and integral non-linearity (INL) are 0.24 and 0.39 LSB, respectively. At 3.2-GS/s operation, the effective number of bits is 4.54 b, and the effective resolution bandwidth is 600 MHz. This ADC achieves figures of merit of 3.07 and 4.30 pJ/conversion-step at 2 and 3.2 GS/s, respectively.

A 1.3-GHz 350-mW Hybrid Direct Digital Frequency Synthesizer in 90-nm CMOS

Abstract: This paper presents a low-power direct digital frequency synthesizer (DDFS) based on a hybrid design with a maximum operating frequency of 1.3 GHz. The proposed hybrid design is capable of extending the resolution of traditional nonlinear digital-to-analog converter (DAC)-based DDFS by adding a linear slope component to the approximated sine wave produced from a nonlinear DAC via an additional linear DAC. With an 11-bit combined DAC, the prototype DDFS produces a minimum spurious free dynamic range (SFDR) of 52 dBc from dc up to Nyquist frequency when clocked at 1.3 GHz. This 90-nm CMOS chip occupies 2 mm2 including bond pads and dissipates 350 mW with a 1.2-V digital supply and 2.5-V analog supply. The FOM of this chip is measured at 1207.9 GHz ·2 ENOB /W .

A 12fJ/conversion-step 8bit 10MS/s asynchronous SAR ADC for low energy radios

Abstract: This paper presents an 8-bit asynchronous SAR ADC for flexible, low energy radios. The prototype in a 90nm CMOS technology achieves an ENOB of 7.7bit at a sampling frequency of 10.24MS/s while consuming 26.3µW from a 1V supply. Excellent power efficiency is achieved by using asynchronous dynamic logic, custom 0.5fF unit capacitors, a low-complexity design and an optimized layout. The measured prototype achieves a FoM of 12fJ/conversion-step, which is a 2.5x improvement over previous state-of-the-art 8-bit converters. Moreover, the fully dynamic design, which is optimized for low-leakage, leads to a standby power consumption of 6nW.

A cryogenic analog to digital converter operating from 300 K down to 4.4 K.

Abstract: This paper presents a cryogenic successive approximation register (SAR) based analog to digital converter (ADC) implemented in a standard 0.35 microm complementary metal oxide semiconductor (CMOS) process. It operates from room temperature down to 4.4 K, achieving 10.47 effective number of bits (ENOB) at room temperature. At 4.4 K, the ADC achieves 8.53 ENOB at 50 kS/s sampling rate with a current consumption of 90 microA from a 3.3 V supply. The ADC utilizes an improved comparator architecture, which performs offset cancellation by using preamplifiers designed for cryogenic operation. The conventional offset cancellation algorithm is also modified in order to eliminate the effect of cryogenic anomalies below freeze-out temperature. The power efficiency is significantly improved compared to the state of the art semiconductor ADCs operating in the same temperature range.

A 0.06mm 2 8.9b ENOB 40MS/s pipelined SAR ADC in 65nm CMOS

Abstract: In 10b SAR ADCs, one of the major design challenges is the large number of capacitors for implementing the capacitor array. A large unit capacitance should be used due to the design constraint of capacitor mismatches and/or layout design rules. As a result, the total capacitance is typically much larger than what is required by kT/C noise. In [1], a 10-bit SAR ADC is presented that achieves an area of 0.075mm2 with a charge redistribution architecture using a small unit capacitance of 10fF, while SNDR is low becasue of using such a small unit capacitance. The charge-sharing SAR proposed in [2] allows a relatively large unit capacitance by reducing the required number of capacitors. However, it requires a large (10pF) S/H capacitor for precise operation. The ADC presented in [3] needs large logic circuits to implement a complex calibration. The converter presented in [4] is a pipelined ADC. The pipelined architecture overcomes the unit capacitance issue of SAR, but the area and the power consumption of the amplifiers are still large.

Digital Radio over Fibre for Future Broadband Wireless Access Network Solution

Abstract: Digital systems are more flexible and environment-process-tolerant than analogue systems. They are more reliable and robust against cross-talk, interference and channel noises, and are capable of covering higher dynamic range than analogue systems. Wideband electronic analogue to digital conversion (ADC) systems have critical problems encountered in high-frequency broadband communication systems that the recent electronic ADCs (EADC) have experienced those such as uncertainty of sampling time. In this paper, an 80Gigasample/s all photonic sampling and quantization ADC and photonic digital to analogue conversion system with six effective number of bits (ENOB) is designed. By using this Photonic ADC (PADC), a digital radio over fibre link for wireless radio frequency (RF) signal transportation over 50 km single mode fibre has been designed whose performance is investigated in this paper.

A hybrid analog-to-digital converter, an image sensor and a method for providing a plurality of ditigal signals

Abstract: A hybrid analog-to-digital converter includes a plurality of converting circuits. Each converting circuit is configured to provide a digital signal based on an analog input signal by performing a successive approximation conversion to obtain, as a result of the successive approximation conversion, a first number of bits of the digital signal, and by subsequently performing a slope conversion based on a common variable reference voltage to obtain a second number of bits of the digital signal, the second number of bits corresponding to a residual between the analog input signal and the result of the successive approximation conversion. The hybrid analog-to-digital converter further includes a common variable reference voltage provider configured to provide to each converting circuit of the plurality of converting circuits the common variable reference voltage.

Systems and methods for vector-based analog-to-digital converter sequential testing

Abstract: A method for providing built-in self test (BiST) for an analog-to-digital converter (ADC) by automatic test equipment (ATE) is described. Output codes are received from the ADC. The output codes are translated to generate a functional pattern. Performance metrics are determined for the ADC using the functional pattern. The ADC may be on a device-under-test (DUT).

A 3-GS/s 5-bit 36-mW flash ADC in 65-nm CMOS

Abstract: A 3-GS/s 5-bit flash ADC is fabricated for millimeter-wave communication systems in 65nm CMOS technology. The proposed foreground calibration method reduces the input-referred DC offset, achieving the resolution of 4.7 ENOB at 200MHz input frequency and keeping more than 4.3 ENOB even at Nyquist. The ADC consumes only 36.2mW including the power of the clock buffer and the resistor ladder from 1-V supply. The ADC has the FoM of 0.6pJ/conv at Nyquist.

Apparatus and method for analog-to-digital converter calibration

Abstract: An analog-to-digital converter (ADC) is provided. The ADC includes a reference voltage generator configured to generate reference voltages, an analog to digital converter core configured to receive an input signal and the reference voltages and to generate a digital signal representative of the input signal, the digital signal having a number of bits, and a controller configured to determine a quality of the input signal, and, based on a quality of the input signal, to control the number of bits of the digital signal and values of the reference voltages.

An on-chip waveform capturing technique pursuing minimum cost of integration

Abstract: An on-chip waveform capturing technique demonstrates 8.5 ENOB and 62.7 dB SFDR at 200 Ms/s for analog signals with 25-MHz bandwidth and 2.5 V rail-to-rail offset DC level, suitable for testing and self diagnosis of a mixed-signal chip. The area of 0.004mm2 in a 90 nm CMOS chip is only required for the integration of probing front end circuitry, with the help of an efficient discretization algorithm on a digital data processing chain involving on-chip logic paths, an off-chip 8 bit micro controller, and PC. Waveform acquisition at the system throughput of 1.9 transaction/point is achieved, by minimizing the number of slow-speed transactions between external measurement equipments and PC.

nth-order multi-bit ΣΔ ADC using SAR quantiser

Abstract: An nth-order multi-bit delta-sigma (ΣΔ) analogue-to-digital converter (ADC) using a successive approximation register (SAR) quantiser is proposed. By exploiting the residue voltage of a multi-bit SAR ADC, the proposed ADC performs as an nth-order noise shaping converter with only one opamp and removes the need for a feedback multi-bit DAC. In addition, the proposed architecture is very reconfigurable and can be implemented as a bandpass ADC.

Distortion Correction in a High-Resolution Time-Stretch ADC Scalable to Continuous Time

Abstract: Distortions caused by system components and by fundamental physical phenomena can limit the performance of photonic time-stretch ADCs. Here we use a combination of time-stretch linearization & equalization, DC-offset subtraction, and operation in a linear propagation regime to improve the signal-to-noise-and-distortion ratio by 17 dB for a 2-channel time-stretch ADC testbed and therein obtain noise-limited performance of 6-7 ENOB over a 10-GHz RF input bandwidth. Time-stretch linearization & equalization corrects for dispersion mismatches among testbed components by applying time-shifts calculated from component group delays to output ADC samples. DC-offset subtraction removes static errors due to insertion loss imbalances and Mach-Zehnder modulator bias offsets. If optical power levels are too high, nonlinear fiber propagation lowers the frequencies of dispersion-induced nulls in the RF transfer function and causes higher-order signal distortions. The 2-channel testbed can be directly scaled to a practical continuous-time system with the addition of more sub-aperture wavelength channels (total of 13 channels and 42 nm of optical bandwidth for a 90 MHz laser repetition rate). Adaptive online and fixed pre-calibrated stitching methods are demonstrated for joining data from one wavelength channel to the next.

A fine-resolution Time-to-Digital Converter for a 5GS/S ADC

Abstract: This paper presents the architecture of a high-speed time-based Analog-to-Digital Converter (ADC) based on voltage-to-time and time-to-digital conversion. A tunable Time-to-Digital Converter (TDC) that is robust against process variation and suitable for embedding within a 3-bit ADC is discussed and its performance evaluated. Simulation shows that when the TDC is designed in a 90nm CMOS process it is capable of a DNL and INL less than ±0.040L5B and ±0.015LSB, respectively, for 9mW of power consumption at 5GS/s with a 6.25ps resolution.

An 8-bit 120-MS/s Interleaved CMOS Pipeline ADC Based on MOS Parametric Amplification

Abstract: This brief presents an 8-bit 120-MS/s time-interleaved pipeline analog-to-digital converter (ADC) fully based on MOS discrete-time parametric amplification. The ADC, fabricated in a 130-nm CMOS logic process, features an active area below 0.12 mm2, where only MOS devices are used. Measurement results for a 20-MHz input signal shows that the ADC achieves 39.7 dB of signal-to-noise ratio, 49.3 dB of spurious-free dynamic range, -47.5 dB of total harmonic distortion, 39.1 dB of signal-to-noise-plus-distortion ratio, and 6.2 bits of peak effective number of bits while consuming less than 14 mW from a 1.2-V supply.

Column parallel single-slope ADC with time to digital converter for CMOS imager

Abstract: We propose a single-slop ADC with a time to digital converter (TDC) that uses a multi-phase clock. Single-slope ADCs have been used as column parallel ADCs for CMOS image sensors. When the TDC with resolution of n bits is adapted to the ADC, the conversion time is reduced by a factor of 2n. Applying the TDC that uses multi-phase-clock signal reduced the number of circuit elements, achieved consistency between the single-slope ADC and the TDC, and realized robust meta-stability. We designed a 12-bit ADC, which consists of the 3-bit TDC and the 9-bit-single-slope ADC, by using a 0.25-µm CMOS process. Through SPICE simulation, we confirmed our single-slop ADC to be more consistent, have more robust meta-stability, and achieve higher-speed ADC operation at 200-MHz clock than the conventional single-slope ADC. The simulated DNL and INL were ±0.25 LSB and ±0.43 LSB.

Maximum likelihood estimation of ADC Parameters

Abstract: Dynamic testing of analog-digital converters (ADC) is a complex task. A possible approach is using a sine wave because it can be generated with high precision. However, in the sine wave fitting method for the test of ADC's, all the available information is extracted from the measured data. Therefore, the estimated ADC parameters (ENOB, linearity errors) are not always accurate enough, and not detailed information is gained about the nonlinearity of the AD

Design of CMOS sampling switch for ultra-low power ADCs in biomedical applications

Abstract: This paper deals with the design of CMOS sampling switch for ultra-low power analog-to-digital converters (ADC) in biomedical applications. General switch design constraints are analyzed, among which the voltage droop due to the subthreshold leakage current constitutes the major error source for low-speed sampling circuits. Based on the analyses, a CMOS sampling switch with leakagereduction has been designed for a 10-bit 1-kS/s successive approximation (SA) ADC in a standard 130 nm CMOS process. Post-layout simulation shows that the ADC with the proposed switch offers an effective number of bits (ENOB) of 9.5 while consuming only 64 nW.

Zero-Crossing-Based Ultra-Low-Power A/D Converters

Abstract: Since the first demonstration of a comparator-based switched-capacitor circuit, analog-to-digital (A/D) converters based on virtual ground detection have made steady and significant progress. Comparators have been replaced by zero-crossing detectors, leading to the development of zero-crossing based circuits for faster speed and lower power. All facets of performance including the sampling rate, effective number of bits, noise floor, and figure-of-merit have improved substantially. This paper focuses on recent implementations of zero-crossing based A/D converters and discusses the technical issues unique to these A/D converters as well as solutions that have been developed to improve their performance and practicality. A series of prototype designs whose performance ranges from 8 bit, 200 MS/s to 12 bit, 50 MS/s are described. The ultimate low power potentials of these A/D converters are compared with various different types of complementary metal-oxide-semiconductor A/D converters from a fundamental thermal noise standpoint.

Power optimized ADC for wireless transceivers

Abstract: An analog-to-digital converter (ADC) of a radio receiver can consume a relatively large amount of power. It is typically desirable to minimize power consumption, particularly with battery-powered devices, such as in wireless receivers. In certain conditions, the effective number of bits (ENOB) required from an ADC of a receiver can vary. The power consumption of certain ADC topologies, such as pipelined converter topologies, can vary with the number of bits. One embodiment dynamically varies the ENOB of an ADC to more optimally consume power. This can extend battery life.