Showing papers on "Effective number of bits published in 2015"

A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18- $\mu{\rm m}$ CMOS for Medical Implant Devices

Abstract: This paper presents a 10-bit ultra-low power successive approximation register (SAR) analog-to-digital converter (ADC) for implantable medical devices. To achieve the nanowatt range power consumption, a novel switching scheme is proposed, which can accomplish the first three comparisons without consuming any energy and thus improve the energy efficiency significantly. In addition, to boost the offset performance of the comparator working under low supply voltage, a detailed theoretical analysis of comparator offset voltages is made. Based on the analysis, the comparator is optimized by only adjusting transistor sizes without any particular offset cancellation. As a result, when the common-mode input voltage varies from 300 mV to 450 mV at a 0.6 V supply, the $3\times\sigma$ offset voltage is optimized to be about 6 mV with a fluctuation of only 0.15 mV, as revealed by Monte Carlo simulations. A prototype of the proposed ADC was fabricated in 0.18 $\mu{\rm m}$ 1P6M CMOS technology, which occupies an active area of only $380\times 430\ \mu{\rm m}^{2}$ . At a 0.6-V supply and 20 kS/s sampling rate, the ADC achieves an SNDR of 58.3 dB and a power consumption of 38 nW, resulting in a figure of merit (FOM) of 2.8 fJ/conversion-step.

A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS

Abstract: This paper presents a 10-bit ultra-low voltage energy-efficient SAR ADC. The proposed merge-and-split (MS) switching effectively reduces DAC switching energy by 83% compared with conventional one without the need of extra reference voltage $({\rm V}_{\rm cm})$ and the issue of common-mode voltage variation. To maintain good input linearity, a new double-bootstrapped sample-and-hold (S/H) circuit is proposed under an ultra-low voltage of 0.3 V. In addition, by employing asymmetric logic in SAR control, the leakage power is reduced with the penalty of slight conversion speed degradation. The test chip fabricated in 90 nm CMOS occupied a core area of 0.03 ${\rm mm}^{2}$ . With a single 0.3 V supply and a Nyquist rate input, the prototype consumes 35 nW at 90 kS/s and achieves an ENOB of 8.38 bit and a SFDR of 78.2 dB, respectively. The operation frequency is scalable up to 2 MS/s and power supply range from 0.3 V to 0.5 V. The resultant FOMs are 1.17-to-1.78 fJ/conv.-step.

Energy efficiency maximization for 5G multi-antenna receivers

Abstract: In a digital communication system, the analog signal that the receiver receives with its radio frequency front end is converted into digital format by using the analog-to-digital converter A/D converter, ADC. Quantisation takes place during the conversion from continuous amplitude signal to discrete amplitude signal, leading inevitably to losses in information which are dependent on the number of bits that is used to represent each sample. Although employing a higher bit resolution reduces the quantisation error, a higher power dissipation of the ADC is incurred at the same time. This trade-off is essential to the energy efficiency of the receiver, which is commonly measured by the number of information bits conveyed per consumed Joule of energy. We investigate, in this work, the adaptation of ADC resolutions of a multi-antenna receiver based on instantaneous channel knowledge, with the goal of maximising receiver energy efficiency. The formulated optimisation is a combinatorial problem, and we propose several algorithms which yield near-optimal solutions. Results from numerical simulations are presented and analysed, which provide guidelines to operation and deployment of the system. Copyright © 2014 John Wiley & Sons, Ltd.

A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC

Abstract: A compact decision-error-tolerant 2b/cycle SAR ADC architecture is presented. Two DACs with different designated functions, SIG-DAC and REF-DAC, are implemented to make the structure compact and to eliminate the sampling skew issue. Use of a nonbinary decision scheme with decision redundancies not only increases the ADC speed with a relaxed DAC settling requirement but also makes the performance robust to reference fluctuations and comparator offset variations. The proposed dynamic register and direct DAC control scheme enhance the conversion speed by minimizing logic delay in the SAR decision loop. The proposed comparator-error detection with digital error correction scheme enhances high-speed ADC performance. A prototype 7b ADC fabricated in a 45 nm CMOS process operates at a sampling rate of 1 GS/s under a 1.25 V supply while achieving a peak SNDR of 41.6 dB and maintaining an ENOB higher than 6 up to 1.3 GHz signal frequency. The FoM under a 1.25 V supply is an 80 fJ/conversion-step with a power consumption of 7.2 mW.

A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC

Abstract: This paper presents an opamp-free solution to implement noise shaping in a successive approximation register analog-to-digital convertor. The comparator noise, incomplete settling error of digital-to-analog convertor and mismatch are alleviated. Designed in a 65 nm CMOS technology, the prototype realizes 58 dB SNDR at 50 MS/s sampling frequency. It consumes 120.7 μW from a 0.8 V supply and achieves a FoM of 14.8 fJ per conversion step.

An 8-bit 100-GS/s Distributed DAC in 28-nm CMOS for Optical Communications

Abstract: An 8-bit 100-GS/s digital-to-analog converter (DAC) using a distributed output topology in 28-nm low-power CMOS for optical communications is presented. The DAC can convert 1-k symbols stored in the 1-kbyte design-for-test on-chip memory cyclically. By interleaving four 25-GS/s return-to-zero DACs, the highest signal frequency of the 100-GS/s DAC is about 25 GHz and the output image is located beyond 75 GHz. The 3-dB bandwidth exceeds 13 GHz at 100 GS/s. The effective number of bits and spurious-free dynamic range ranges from 5.3 bit and 41 dB to 3.2 bit and 27 dB from dc up to 24.9 GHz at 100 GS/s, respectively. Transmission rates of 120 and 45 Gb/s are obtained in an electrical and an optical back-to-back experiment, respectively. The DAC test chip consumes 2.5 W from a power supply with multiple outputs of 1.1, 1.5, and 2 V.

26.2 A 5.5fJ/conv-step 6.4MS/S 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme

Abstract: Wireless standards, e.g., 802.15.4g, need high-resolution ADCs (>10b) with very low power and MS/s sampling rates. The SAR ADC is well known for its excellent power efficiency. However, its intrinsic accuracy (DAC matching) is limited up to 10 to 12b in modern CMOS technologies [1]. Scaling up the device dimensions can improve matching but it deteriorates power-efficiency and speed. Alternatively, calibrations [2-5] are introduced to correct errors (e.g., comparator offset and capacitor mismatch) and push the SNDR beyond 62dB. However, most of the calibrations [2-4] are implemented off-chip and the power for the calibration circuit is relatively high when implemented on-chip. Foreground calibration [4-5] is an alternative but is sensitive to environmental changes. We report a low-power fully automated on-chip background calibration that uses a redundancy-facilitated error-detection-and-correction scheme. Thanks to the low-power calibration, this ADC achieves an ENOB of 10.4b and a power efficiency of 5.5fJ/conv-step at 6.4MS/S.

An All-Digital Scalable and Reconfigurable Wide-Input Range Stochastic ADC Using Only Standard Cells

Abstract: An all-digital programmable and reconfigurable stochastic analog-to-digital converter (ADC) is presented in this work. This ADC directly benefits from scaling by using only digital gates and relying on an increased mismatch between minimum‐sized transistors. The programmability and reconfigurability are achieved by dividing the design into eight channels. The mean of each channel is set independently using a digitally generated analog reference voltage with a 10-bit control word. The output of each channel is linearized using Gaussian linear interpolation. The entire ADC is written in Verilog and synthesized into digital standard cells using regular digital design tools. Fabricated in a 130-nm complementary metal–oxide–semiconductor process, the ADC covers signal-to-noise and distortion ratio from 28 to 34.9 dB with a programmable differential input range of 400–800 mVpp at 140 MS/s and 0.7-V supply.

A Reconfigurable 5-to-14 bit SAR ADC for Battery-Powered Medical Instrumentation

Abstract: In battery-powered medical instrumentation, the resolution and signal bandwidth of analog-to-digital converters (ADCs) have to be adapted to the needs of the application to avoid power wastage. This paper presents a reconfigurable successive approximation register (SAR) ADC implemented in 130 nm CMOS that resolves 5–14 bit with a maximum achievable effective number of bits (ENOB) of 13.5 using non-subtractive dither. In the proposed ADC design, the power consumption can be traded for accuracy to improve the energy efficiency and extend its application range, while reducing system integration complexity. A figure-of-merit (FoM) of 59 fJ/conversion is achieved at 1.2 V supply and the converter occupies an area of 0.42 ${\rm mm}^{2}$ . Measurement results of the ADC integrated in a multi-channel analog front-end (AFE) circuit show the suitability of the ADC for portable medical monitoring devices.

Experimental Demonstration of Real-Time High-Level QAM-Encoded Direct-Detection Optical OFDM Systems

Abstract: In this paper, high-level quadrature amplitude modulation (QAM)-encoded real-time orthogonal frequency division multiplexing (OFDM) transceivers are implemented with two field programmable gate arrays and high-resolution digital-to-analog converter (DAC) and analog-to-digital converter (ADC). Some key digital signal processing (DSP) algorithms for real-time direct-detection optical OFDM (DDO-OFDM) system are presented and described in detail. To improve the effective number of bits of ADC and reduce quantization noise, the DAC operates at 5 GS/s with an oversampling factor of 2. Meanwhile, the optimal digital clipping ratio at the transmitter is also investigated by numerical simulation to optimize the performance of the real-time transmitter. The results show that the real-time measured BERs after 10-km SSMF are below the hard-decision forward error correction threshold of $3.8 \times 10^{-3}$ . For comparison, the off-line BER performance is also analyzed using off-line DSP approaches. It shows that there is a negligible power penalty between the offline and real-time processing results. To the best of our knowledge, we have achieved the highest modulation format (1024-QAM) for real-time optical OFDM systems.

A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS

Abstract: This paper presents a 12-bit energy-efficient successive approximation register analog-to-digital converter (ADC). By incorporating the proposed capacitor-swapping technique, which eliminates the problematic MSB mismatch transition of a binary-weighted capacitor digital-to-analog converter, the 12-bit linearity of the ADC is achieved without increasing the capacitor size for improved matching. The small capacitor size results in low power consumption. In addition, an on-the-fly programmable dynamic comparator is used for quick comparisons with low noise contributions within the limited power budget. The ADC is fabricated using a 110-nm CMOS process. It consumes 16.47 $\mu{\rm W}$ from a 0.9-V supply at a conversion-rate of 1 MS/s. The measured DNL and INL are within 0.3 LSB and 0.56 LSB, respectively. The measured SNDR and SFDR are at 67.3 dB and 87 dB, respectively. The ENOB performance is 10.92 b, which is equivalent to a figure-of-merit of 8.47 fJ/conversion-step.

Linearization Through Dithering: A 50 MHz Bandwidth, 10-b ENOB, 8.2 mW VCO-Based ADC

Abstract: Non-linear voltage-to-frequency characteristic of a voltage-controlled oscillator (VCO) severely curtails the dynamic range of analog-to-digital converters (ADCs) built with VCOs. Typical approaches to enhance the dynamic range include embedding the VCO-based ADC in a $\Delta\Sigma$ loop or to post-process the digital data for calibration, both of which impose significant power constraints. In contrast, in this work the VCO-based ADC is linearized through a filtered dithering technique, wherein the VCO-based ADC is used as a fine stage that processes the residue from a coarse stage in a 0–1 MASH structure. The proposed filtered dithering technique conditions the signal to the VCO input to appear as white noise thereby eliminating spurious signal content arising out of the VCO nonlinearity. The work resorts to multiple other signal processing techniques to build a high-resolution, wideband prototype, in 65 nm complementary metal-oxide semiconductor (CMOS), that achieves 10 effective number of bits (ENOB) in digitizing signals with 50 MHz bandwidth consuming 8.2 mW at a figure of merit (FoM) of 90 fJ/conv.step.

A 0.8-V, 1-MS/s, 10-bit SAR ADC for Multi-Channel Neural Recording

Abstract: This paper presents a 10-bit single-ended SAR ADC suitable for multi-channel neural recording. The proposed ADC introduces several power saving techniques to boost the energy efficiency. The ADC is built with on-chip common-mode buffer for input tracking, which is reused as the pre-amplifier of a current-mode comparator during conversion. A small capacitor is inserted between the amplifier and the capacitive DAC array in order to reduce the capacitive load on the amplifier. A split capacitor array with dual thermometer decoders is proposed to reduce the switching energy. Implemented in 0.13- $\mu{\rm m}$ CMOS technology, the ADC achieved a maximum differential nonlinearity (DNL) of $-$ 0.33/ $+$ 0.56 LSB, maximum integral nonlinearity (INL) of $-$ 0.61/ $+$ 0.55 LSB, effective number-of-bits (ENOB) of 8.8, and a power consumption of 9- $\mu{\rm W}$ .

26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS

Abstract: Recently reported high-speed ADCs have mostly taken advantage of time-interleaved (TI) architectures with low-power SAR ADCs for their sub-channels. However, given that the TI architecture needs to satisfy matching requirements between channels, the circuit complexity arising from the calibrations has often become a considerable burden. In order to reduce the number of channels in TI SAR ADCs, a flash-assisted TI (FATI) SAR structure [1] can be utilized to enhance the conversion speed of a sub-channel SAR ADC due to the multi-bit MSBs from a front-end flash ADC. In addition, because the codes from each SAR ADC embed the timing skew information of the corresponding channel, the structure can extract timing skew information in an efficient manner [2]. Despite these advantages of FATI SAR ADCs, as the required conversion rate increases, the power consumption of the front-end flash ADC becomes significant, which reduces the efficiency. In addition, if the target speed is higher than the frequency achievable by a single flash ADC, the FATI SAR ADC should be time-interleaved with multiple flash ADCs. The timing skew calibration scheme reported in [2] cannot be applied in this case. Considering these issues, this work introduces an advanced FATI SAR ADC with a folding-flash (F-flash) ADC that reduces the power burden placed upon a flash ADC. In addition, 2× time interleaving is applied in an effort to lower the conversion rate of the flash ADC (time-interleaved FATI SAR ADC). The offset and timing skew of each channel are calibrated in the background.

An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers

Abstract: This paper presents a 0.55 V, 7 bit, 160 MS/s pipeline ADC using dynamic amplifiers. In this ADC, high-speed open-loop dynamic amplifiers with a common-mode detection technique are used as residue amplifiers to increase the ADC's speed, to enhance the robustness against supply voltage scaling, and to realize clock-scalable power consumption. To mitigate the absolute gain constraint of the residue amplifiers in a pipeline ADC, the interpolated pipeline architecture is employed to shift the gain requirement from absolute to relative accuracy. To show the new requirements of the residue amplifiers, the effects of gain mismatch and nonlinearity of the dynamic amplifiers are analyzed. The 7 bit prototype ADC fabricated in 90 nm CMOS demonstrates an ENOB of 6.0 bits at a conversion rate of 160 MS/s with an input close to the Nyquist frequency. At this conversion rate, it consumes 2.43 mW from a 0.55 V supply. The resulting FoM of the ADC is 240 fJ/conversion-step.

A Charge Recycling SAR ADC With a LSB-Down Switching Scheme

Abstract: This paper presents a new energy efficient successive approximation analog-to-digital converter (ADC) using a charge recycling and LSB-down switching scheme for the capacitive digital-to-analog converter (CDAC). Compared to the conventional binary weighed CDAC, the proposed technique exhibits a 95% reduction in switching energy, a 50% reduction in capacitor area, and with 30% reduction in nonlinearity under the same unit capacitor size and matching condition. The improvement on the switching energy consumption is the best among reported CDAC switching techniques. To validate the technique, a prototype of 10-bit ADC is fabricated in a 0.13 $\mu{\rm m}$ CMOS technology using standard capacitors. With a unit capacitor size of 30 fF, the ADC consumes 15.6 $\mu{\rm W}$ from a 0.5 V digital supply and a 1 V analog supply. The measured signal-to-noise-plus- distortion ratio is 54.6 dB $({\rm ENOB}=8.8)$ at 1.1 MS/s. The FOM is 31.8 fJ/conv.-step, which is among the best when normalized to the same unit capacitor size.

Methods and apparatus for reducing timing-skew errors in time-interleaved analog-to-digital converters

Abstract: A time-interleaved (TI) analog-to-digital converter (ADC) architecture employs a low resolution coarse ADC channel that samples an input analog signal at a Nyquist rate and facilitates background calibration of timing-skew error without interrupting normal operation to sample/convert the input signal. The coarse ADC channel provides a timing reference for multiple higher resolution TI ADC channels that respectively sample the input signal at a lower sampling rate. The coarse ADC digital output is compared to respective TI ADC digital outputs to variably adjust in time corresponding sampling clocks of the TI ADC channels so as to substantially align them with the sampling clock of the coarse ADC channel, thus reducing timing-skew error. In one example, the coarse ADC output provides the most significant bits (MSBs) of the respective TI ADC digital outputs to further improve conversion speed and reduce power consumption in these channels.

Highly Linear Broadband Photonic-Assisted Q-Band ADC

Abstract: A highly linear broadband photonic-assisted analog-to-digital converter (ADC) based on high-frequency optical sampling utilizing a dual output Mach–Zehnder modulator operating with signal frequencies up to 50 GHz is presented. The pulses employed in the optical sampling were generated by a cavity-less pulse source operated at 10 GHz in preference to conventional mode-locked lasers. The optical sampling front-end greatly extends the operational frequency range of the Nyquist limited electronic digitization back-end. The performance of the sampling system is characterized with 7.1 effective number of bits (ENOBs) at 40 with 5 GHz fully accessible bandwidth, and greater than 99 dB·Hz2/3 spurious free dynamic range for the 30–40 GHz frequency range. Furthermore, more than 8 ENOB was achieved by reducing the effective bandwidth to 1 GHz with a digital filter, demonstrating the additional advantage of using a higher sampling rate compared to previous demonstrations. A new figure of merit of photonic-assisted sub-sampled ADCs is also presented accompanied with a comparison to previous implementations.

“Split ADC” Background Linearization of VCO-Based ADCs

Abstract: A lookup-table digital correction technique using “split ADC” calibration is used for linearization of VCO-based ADCs. Simulation results in a 45 nm CMOS process targeting 10 b and 12 b resolutions show ENOB of 9.58 b and 11.5 b, with convergence times for background calibration adaptation of 380 ms and 5.7 s, respectively. The background LMS procedure is tolerant of different input signals and provides linearity calibration over the range covered by the input signal excursion. An input dither of 3% of the ADC reference enables absolute accuracy in scale factor calibration. Design tradeoffs related to the VCO V-to- $f$ characteristic, lookup table size, and convergence properties of the LMS adaptation loop are discussed.

A Submicrowatt Implantable Capacitive Sensor System for Biomedical Applications

Abstract: This brief presents a submicrowatt, offset-free, and implantable system for a biomedical capacitive sensor. The system is powered by a 13.56-MHz radio frequency signal and performs sensor signal amplification, analog-to-digital conversion, and load-shift keying uplink data transmission within 640 $\mu\hbox{s}$ . An ultralow-power capacitance-to-digital converter (CDC) is designed by replacing a power-hungry operational amplifier with a subthreshold inverter in a switched-capacitor amplifier (SC-amp) . A fast-response-gain compensation method is employed to reduce the gain error of the SC-amp while achieving high energy efficiency for the CDC. To eliminate the offset, a two-step autocalibration is applied. The application-specific integrated circuit is implemented in the Taiwan Semiconductor Manufacturing Company 90-nm complementary metal–oxide–semiconductor technology, and the whole system achieves an 8.02 effective number of bits with 9-bit linearity while consuming only 5.5 $\mu\hbox{W}$ .

A 1.2 V 2.64 GS/s 8 bit 39 mW Skew-Tolerant Time-interleaved SAR ADC in 40 nm Digital LP CMOS for 60 GHz WLAN

Abstract: A clock-skew tolerant 8-bit 16x time-interleaved (TI) semi-synchronous SAR ADC with switching-energy efficient hybrid resistive-capacitive DAC is presented that meets $WiGig$ standard requirements with only background offset and gain calibrations. Skew tolerance is achieved by using a “correct-by-construction,” timing-calibration-free global bottom-plate sampling scheme. The ADC achieves a sampling rate of 2.64 GS/s while maintaining an ENOB of over 6 bits in the entire Nyquist band. The 40 nm LP CMOS design dissipates 39 mW from 1.2 V. The TI-SAR ADC characterized with an integrated receiver front-end achieves $-$ 21.44 dB EVM at sensitivity with a QAM16 signal.

Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS

Abstract: This paper presents the design of a fast-settling reference voltage buffer (RVBuffer) which is used to buffer the high reference voltage in a 10-bit, 50 MS/s successive approximation register (SAR) ADC implemented in 65 nm CMOS. Though numerous publications on SAR ADCs have appeared in recent years, the role of RVBuffers in ensuring ADC performance, the associated design challenges and impact on power and FoM of the entire ADC have not been discussed in-depth. In this work, the speed limitation on precise settling of the digital-to-analog converter voltage (DAC) in a SAR ADC imposed by parasitic inductances of the bondwire and PCB trace is explained. The crucial design parameters for the reference voltage buffer in the context of the SAR ADC are derived. Post-layout simulation results for the RVBuffer are provided to verify settling-time, noise and PSRR performance. In post-layout simulation which includes the entire pad frame and associated parasitics, the SAR ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.

A 100-nW 9.1-ENOB 20-kS/s SAR ADC for Portable Pulse Oximeter

Abstract: This brief presents an energy-efficient 10-bit accuracy with 20-kS/s successive approximation register analog-to-digital converter for portable pulse oximeter. A data-dependent capacitor reset (DDCR) switching scheme for the capacitive digital-to-analog converter (CDAC) to reduce the average switching energy and the number of unit capacitors is proposed and implemented. Compared with the conventional capacitor switching scheme for CDACs, the proposed DDCR switching scheme reduces the average switching energy and the total number of unit capacitors by 97% and 75%, respectively. We achieved a signal-to-noise-and-distortion ratio of 56.5 dB and a spurious-free dynamic range of 64.7 dBc at the Nyquist input frequency. The measured peak differential and integral nonlinearities are 0.44 and 0.58 least significant bit, respectively. The figure of merit is 9.1 fJ/conversion-step. The prototype, fabricated in the 0.11- $\mu\mbox{m}$ CMOS process, occupies 0.033 mm2.

A 13-ENOB, 5 MHz BW, 3.16 mW multi-bit continuous-time ΔΣ ADC in 28 nm CMOS with excess-loop-delay compensation embedded in SAR quantizer

Abstract: A 13-ENOB, 5 MHz BW, 3.16 mW 3-bit continuous-time ΔΣ ADC sampling at 432 MHz is presented. For power efficiency, this design utilizes a hybrid feedback feed-forward loop topology with SAR quantizer, feed-forward compensated amplifiers, and push-pull DACs. Further power efficiency is gained by performing excess-loop-delay compensation (ELDC) using the SAR quantizer SC-DAC, which reduces power overhead from ELDC to a negligible level. A 94 dB SFDR is achieved through feedback-DAC calibration. The 0.066 mm2 design is fabricated in 28 nm CMOS and achieves FoMs of 36.4 fJ/step and 175.9 dB.

A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process

Abstract: In this paper, we present a single-bit clock-less asynchronous delta–sigma modulator (ADSM) operating at just 0.25 V power supply. Several circuit approaches were employed to enable such low-voltage operation and maintain high performance. One approach involved utilizing bulk-driven transistors in subthreshold region with transconductance-enhancement topology. Another approach was to employ distributed transistor layout structure to mitigate the effect of low output impedance due to halo drain implants employed in today’s digital CMOS process. The ADSM achieved a characteristic center frequency of 630 Hz. It had an effective signal-to-noise-plus-distortion ratio (SNDR) of 58 dB or effective number of bits (ENOB) 9 b and just 28-nW power dissipation. A detailed analytical model capturing the effect of nonidealities of the individual circuit components is also presented for the first time with a close agreement with experimental results.

A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction

Abstract: This paper presents a power-efficient SNR enhancement technique for SAR ADCs. By accurately estimating the conversion residue, it can suppress both comparator noise and quantization error. Thus, it allows the use of a noisy low-power comparator and a relatively low resolution DAC to achieve high resolution. The proposed technique has low hardware complexity, requiring no change to the standard ADC operation except for repeating the LSB comparisons. A prototype ADC is designed in 65nm CMOS. Its SNR is improved by 7dB with the proposed technique. Overall, it achieves 10.5-b ENOB while operating at 100kS/s and consuming 645nW from a 0.7V power supply.

An 8-bit, 10 KS/s, $$1.87\upmu \text {W}$$1.87μW Successive Approximation Analog to Digital Converter in $$0.25\,\upmu \hbox {m}$$0.25μm CMOS Technology for ECG Detection Systems

Abstract: This paper presents an 8-bit successive approximation analog to digital converter (SA-ADC) employing a mostly digital implementation for portable Electrocardiogram (ECG) detection systems. At 10 K samples/s, the proposed SA-ADC consumes $$1.87\,\upmu \hbox {W}$$1.87μW from a 1 V power supply. The layout and extraction of the proposed SA-ADC are done using L-edit and simulated using TSMC $$0.25\,\upmu \hbox {m}$$0.25μm technology file on Pspice. According to the simulation results, the SA-ADC has a signal-to-noise ratio of 57 dB, peak spurious-free dynamic range of 41 dB, and a signal-to-noise-and-distortion ratio of 40.5 dB for a 200 Hz---$$500\hbox {mV}_{\mathrm{pp}}$$500mVpp input sine wave. In addition to that, the SA-ADC has effective number of bits of 6.5-bits, an effective resolution bandwidth of 1.5 kHz and a figure of merit of 6.85 pJ/Conversion step. The digitized ECG signal is precisely reconstructed using a novel reconstruction circuit. These results show that the proposed SA-ADC in $$0.25\,\upmu \hbox {m}$$0.25μm technology is a good candidate for ECG detection systems.

Design of a low-noise, high power efficiency neural recording front-end with an integrated real-time compressed sensing unit

Abstract: This paper presents a 12-channel, low-power, high efficiency neural signal acquisition front-end for local field potential and action potential signals recording. The proposed neural front-end integrates low noise instrumentation amplifiers, low-power filter stages with configurable gain and cut-off frequencies, a successive approximation register (SAR) ADC, and a realtime compressed sensing processing unit. A capacitor coupled instrumentation amplifier integrated input impedance boosting has been designed, dissipating 1μA quiescent current. An input referred noise of 1.63μV was measured in the frequency band of 1Hz to 7kHz. The noise efficiency factor (NEF) of the amplifier is 0.76. The SAR ADC achieves an ENOB of 10.6-bit at a sampling rate of 1MS/s. A compressed sensing processing unit with configurable compression ratio, up to 8x, was integrated in the design. The design has been fabricated in 180nm CMOS, occupying 4.5mm×1.5mm silicon area. A portable neural recorder has been built with the custom IC and a commercial low-power wireless module. A 4.6g lithium battery supports the device for a continuous compressed sensing recording up to 70 hours.

Simplified 2-bit photonic digital-to-analog conversion unit based on polarization multiplexing

Abstract: A 2-bit photonic digital-to-analog conversion unit is proposed and demonstrated based on polarization multiplexing. The proposed 2-bit digital-to-analog converter (DAC) unit is realized by optical intensity weighting and summing, and its complexity is greatly reduced compared with the traditional 2-bit photonic DACs. Performance of the proposed 2-bit DAC unit is experimentally investigated. The established 2-bit DAC unit achieves a good linear transfer function, and the effective number of bits is calculated to be 1.3. Based on the proposed 2-bit DAC unit, two DAC structures with higher (>2) bit resolutions are proposed and discussed, and the system complexity is expected to be reduced by half by using the proposed technique. © 2015 Society of