Showing papers on "Effective number of bits published in 2017"

Hybrid Architectures With Few-Bit ADC Receivers: Achievable Rates and Energy-Rate Tradeoffs

Abstract: Hybrid analog/digital architectures and receivers with low-resolution analog-to-digital converters (ADCs) are two low power solutions for wireless systems with large antenna arrays, such as millimeter wave and massive multiple-input multiple-output systems. Most prior work represents two extreme cases in which either a small number of radio frequency (RF) chains with full-resolution ADCs, or low-resolution ADC with a number of RF chains equal to the number of antennas is assumed. In this paper, a generalized hybrid architecture with a small number of RF chains and a finite number of ADC bits is proposed. For this architecture, achievable rates with channel inversion and singular value decomposition-based transmission methods are derived. Results show that the achievable rate is comparable to that obtained by full-precision ADC receivers at low and medium SNRs. A trade-off between the achievable rate and power consumption for the different numbers of bits and RF chains is devised. This enables us to draw some conclusions on the number of ADC bits needed to maximize the system energy efficiency. Numerical simulations show that coarse ADC quantization is optimal under various system configurations. This means that hybrid combining with coarse quantization achieves better energy-rate trade-off compared with both hybrid combining with full-resolutions ADCs and 1-bit ADC combining.

Low-Frequency Noise and Offset Rejection in DC-Coupled Neural Amplifiers: A Review and Digitally-Assisted Design Tutorial.

Abstract: We review integrated circuits for low-frequency noise and offset rejection as a motivation for the presented digitally-assisted neural amplifier design methodology. Conventional AC-coupled neural amplifiers inherently reject input DC offset but have key limitations in area, linearity, DC drift, and spectral accuracy. Their chopper stabilization reduces low-frequency intrinsic noise at the cost of degraded area, input impedance and design complexity. DC-coupled implementations with digital high-pass filtering yield improved area, linearity, drift, and spectral accuracy and are inherently suitable for simple chopper stabilization. As a design example, a 56-channel 0.13 [Formula: see text] CMOS intracranial EEG interface is presented. DC offset of up to ±50 mV is rejected by a digital low-pass filter and a 16-bit delta-sigma DAC feeding back into the folding node of a folded-cascode LNA with CMRR of 65 dB. A bank of seven column-parallel fully differential SAR ADCs with ENOB of 6.6 are shared among 56 channels resulting in 0.018 [Formula: see text] effective channel area. Compensation-free direct input chopping yields integrated input-referred noise of 4.2 μVrms over the bandwidth of 1 Hz to 1 kHz. The 8.7 [Formula: see text] chip dissipating 1.07 mW has been validated in vivo in online intracranial EEG monitoring in freely moving rats.

A 0.7-V 0.6- $\mu \text{W}$ 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction

Abstract: This paper presents a power-efficient noise reduction technique for successive approximation register analog-to-digital converters (ADCs) based on the statistical estimation theory. It suppresses both comparator noise and quantization error by accurately estimating the ADC conversion residue. It allows a high signal-to-noise ratio (SNR) to be achieved with a noisy low-power comparator and a relatively low resolution digital-to-analog converter (DAC). The proposed technique has low hardware complexity, requiring no change to the standard ADC operation except for repeating the least significant bit (LSB) comparisons. Three estimation schemes are studied and the optimal Bayes estimator is chosen for a prototype 11-b ADC in 65-nm CMOS. The measured SNR is improved by 7 dB with the proposed noise reduction technique. Overall, it achieves 10.5-b effective number of bits while operating at 100 kS/s and consuming $0.6~\mu \text{W}$ from a 0.7-V power supply.

A reconfigurable cryogenic platform for the classical control of quantum processors.

Abstract: The implementation of a classical control infrastructure for large-scale quantum computers is challenging due to the need for integration and processing time, which is constrained by coherence time. We propose a cryogenic reconfigurable platform as the heart of the control infrastructure implementing the digital error-correction control loop. The platform is implemented on a field-programmable gate array (FPGA) that supports the functionality required by several qubit technologies and that can operate close to the physical qubits over a temperature range from 4 K to 300 K. This work focuses on the extensive characterization of the electronic platform over this temperature range. All major FPGA building blocks (such as look-up tables (LUTs), carry chains (CARRY4), mixed-mode clock manager (MMCM), phase-locked loop (PLL), block random access memory, and IDELAY2 (programmable delay element)) operate correctly and the logic speed is very stable. The logic speed of LUTs and CARRY4 changes less then 5%, whereas the jitter of MMCM and PLL clock managers is reduced by 20%. The stability is finally demonstrated by operating an integrated 1.2 GSa/s analog-to-digital converter (ADC) with a relatively stable performance over temperature. The ADCs effective number of bits drops from 6 to 4.5 bits when operating at 15 K.

Pseudo Asynchronous Level Crossing adc for ecg Signal Acquisition

Abstract: A new pseudo asynchronous level crossing analogue-to-digital converter ( adc ) architecture targeted for low-power, implantable, long-term biomedical sensing applications is presented. In contrast to most of the existing asynchronous level crossing adc designs, the proposed design has no digital-to-analogue converter ( dac ) and no continuous time comparators. Instead, the proposed architecture uses an analogue memory cell and dynamic comparators. The architecture retains the signal activity dependent sampling operation by generating events only when the input signal is changing. The architecture offers the advantages of smaller chip area, energy saving and fewer analogue system components. Beside lower energy consumption the use of dynamic comparators results in a more robust performance in noise conditions. Moreover, dynamic comparators make interfacing the asynchronous level crossing system to synchronous processing blocks simpler. The proposed adc was implemented in $0.35\,{\mu }{\text{m}}$ complementary metal-oxide-semiconductor ( cmos ) technology, the hardware occupies a chip area of $0.0372\,\mathrm{mm}^2$ and operates from a supply voltage of $1.8\,{\text{V}}$ to $2.4\,{\text{V}}$ . The adc 's power consumption is as low as $0.6\,{\mu }\mathrm{W}$ with signal bandwidth from $0.05\,{\text{Hz}}$ to $1\,{\text{kHz}}$ and achieves an equivalent number of bits ( enob ) of up to 8 bits.

When Are Low Resolution ADCs Energy Efficient in Massive MIMO

Abstract: Massive MIMO (MaMI) is often promoted as a technology that will enable the use of low-quality, cheap hardware. One particular component that has been in the focus of MaMI-related research is the analog-to-digital converter (ADC), and use of very low-resolution ADCs has been proposed. However, studies about whether this strategy is justified from an energy-efficiency point of view have largely been inconclusive. In this paper, we choose system setup and models that reflect the hardware implementation reality as close as possible and perform a parametric analysis of uplink energy efficiency as a function of ADC resolution. If antenna scaling and decrease of ADC resolution are considered independently, the energy efficiency is shown to be maximized at intermediate ADC resolutions, typically in the range of 4–8 bits. Moreover, optimal ADC resolution does not decrease when more antennas are used except in some specific cases, and when it does, the decrease is approximately logarithmic in the number of antennas. In the case when antenna scaling and ADC degradation are coupled through a constant-performance constraint, it is shown that energy efficiency cannot improve with reduced bit resolution unless the power consumption of blocks other than ADCs scales down with the upscaling of antennas at a fast enough rate. Altogether it is concluded that in MaMI, intermediate ADC resolutions are optimal in energy efficiency sense, and, except in some special cases, scaling up the antennas to very large numbers does not change this conclusion.

A 13b-ENOB 173dB-FoM 2 nd -order NS SAR ADC with passive integrators

Abstract: This paper presents a low-power 2nd-order noise-shaping (NS) SAR ADC. Instead of using power-hungry op-amps, it uses switches and capacitors to make passive integrators for noise shaping. The overall architecture is simple and the NS order can be easily reconfigured from 0 to 2. A prototype chip is fabricated in a 40nm CMOS process. With 2nd-order NS, the chip consumes 143μW power at 1.1V and 8.4MS/s. At an OSR of 16, SNDR is 80dB and the Schreier FoM is 173dB.

40 GSample/s All-Optical Analog to Digital Conversion With Resolution Degradation Prevention

Abstract: In this letter, we report the experimental demonstration of a 40 GSample/s all-optical analog to digital converter (ADC). The proposed all-optical ADC consists of optical quantization and coding processes based on intensity-to-wavelength conversion by soliton self-frequency shift with an optical sampling process using an ultrastable optical pulse train. A 5-GHz sinusoidal analog input signal was successfully converted to a digitized output signal in real time with no degradation of resolution. (High sampling rate operation may lead to resolution degradation due to the reduction of pulse peak power and the narrowing of the interval between adjacent pulses.) To evaluate system performance, we estimated the effective number of bits from the experimental results as 3.79 b.

A 0.3 V 10-bit SAR ADC With First 2-bit Guess in 90-nm CMOS

Abstract: This paper presents the design and implementation of a 10-bit ultra-low voltage energy-efficient successive approximation register (SAR) analog-to-digital converter (ADC). The proposed first 2-bit guess (F2G) scheme reduces the DAC switching energy by 90% and improves the DNL and INL by $\sqrt {3} {/2}$ in theory compared with the conventional approach. By employing majority-vote comparison at the conversions of LSBs, the noise requirement of comparator can be relaxed by half. With the segmented and bundled routing, the parasitic capacitors of bottom-plates of DAC array are reduced to improve power efficiency and speed. Implemented in 90-nm CMOS technology, the test chip occupied a core area of 0.03 mm2. The prototype consumes 67.3 nW at 150 kS/s from a single 0.3 V supply voltage and achieves an ENOB of 8.85 bits and an SFDR of 70.7 dB at Nyquist input, respectively. The resultant Walden’s FoM and Schreier’s FoM are 0.97 fJ/conv.-step and 175.5 dB, respectively.

A Precision Capacitance-to-Digital Converter With 16.7-bit ENOB and 7.5-ppm/°C Thermal Drift

Abstract: This paper presents a high-precision capacitance-to-digital converter (CDC) for displacement measurement in advanced industrial applications, based on a charge-balancing third-order delta–sigma modulator. To achieve high precision, this CDC employs a precision external resistive reference and a quartz-oscillator-based time reference instead of a reference capacitor. To minimize the error contribution of the CDC circuitry, various precision circuit techniques, such as chopping and auto-zeroing, are applied at both system and circuit level. Measurement results of the prototype realized in 0.35- $\mu \text{m}$ CMOS technology show that the CDC achieves an rms resolution of 42 aF across a capacitance range from 6 to 22 pF, corresponding to an effective number of bits (ENOB) of 16.7 bit. The conversion time for one measurement is 10.5 ms, during which the CDC consumes 230 $\mu \text{A}$ from a 3.3-V single supply. The measured thermal stability is within ±7.5 ppm/°C across a temperature range from 20 °C to 70 °C, which represents a significant improvement compared to the state of the art. After a two-point calibration, all ten measured samples from one batch show absolute accuracy below ±25 fF across the entire capacitance measurement range.

Optimization of Mixed-ADC Multi-Antenna Systems for Cloud-RAN Deployments

Abstract: We propose a mixed analog-to-digital converter ADC (mixed-ADC) structure for a cloud-RAN system, where a single-antenna user terminal communicates with a multi-antenna remote radio head (RRH). In the proposed structure, the RRH is equipped with a mixed-ADC pool that includes multiple ADC units with various resolutions. In this pool, the RRH selects the appropriate ADCs and connects the selected ADCs to each antenna to quantize the received signals; thereby each antenna can have a different resolution ADC. The fronthaul capacity is limited, so that the sum of the bits produced in the selected ADCs is also limited. To maximize the spectral efficiency or the energy efficiency of such a system, we propose algorithms for ADC resolution selection based on an approximation of the generalized mutual information in the low signal-to-noise regime. In the proposed algorithms, we show that for spectral efficiency, using high-resolution ADC on the strong channels is beneficial. The results for energy efficiency maximization are similar, though the largest resolutions are reduced to save power. The simulations show that the proposed method provides significant performance improvement.

A 10-b 2b/cycle 300MS/s SAR ADC with a single differential DAC in 40nm CMOS

Abstract: This paper presents a 2b/cycle hybrid successive­approximation-register (SAR) analog-to-digital-converter (ADC) architecture with only 1 differential capacitor-DAC (CDAC). Unlike prior multi-bit/cycle SAR works that make use of only the DAC differential mode (DM) voltage, the proposed architecture exploits both the DM and the common mode (CM). By using two degrees of freedom, the proposed ADC can generate 3 comparison levels needed for 2b/cycle without requiring extra DAC arrays. Eliminating extra DAC arrays reduces hardware cost, area, and power. The proposed SAR ADC takes advantage of 1b/cycle conversion mode and sufficient redundancy to address problems of multi-bit/cycle conversions, such as unmatched comparator offsets, kickback noise, and comparator input CM voltage variation. Reconfiguration to 1b/cycle is easily done by disabling the unneeded comparators for 1b/cycle conversion. A 10b prototype ADC is fabricated in 40nm LP CMOS process. It achieves peak 8.5b ENOB at sampling frequency of 300MS/s and consumes 2.1mW, leading to a FoM of 19.3fJ/conv-step.

A 12-b ENOB 2.5-MHz BW VCO-Based 0-1 MASH ADC With Direct Digital Background Calibration

Abstract: This paper presents a scaling friendly mostly digital voltage-controlled-oscillator (VCO)-based 0-1 multistage noise shaping (MASH) analog-to-digital converter. A novel background calibration technique corrects conversion errors due to VCO linear gain drift, residue generating digital-to-analog converter mismatches, and nonlinearity of the VCO voltage-to-frequency conversion. The proposed architecture minimally modifies the basic 0-1 MASH architecture and directly calibrates the main VCOs without relying on replica matching. A redundant first-stage coarse quantizer enables fast error estimation in the digital domain. A 12-b prototype implemented in 180-nm CMOS achieves 12-b ENOB over 2.5 MHz and consumes 4.8 mW from a 1.8 V supply.

28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique

Abstract: Wireless standards, e.g. 802.11ac Wave 2 and 802.11ax draft, aim to boost user throughput to cope with growing data traffic. High-speed (f s >100MS/s) and high-resolution (ENOB>9.5b) ADCs are essential for leading-edge wireless SoCs, given the bandwidth and PAPR specifications. Also, low power dissipation (FoM<20fJ/conv) is crucial for mobile applications. A number of pipelined-SAR ADCs have been presented which satisfy these design targets [1–3]. However, in deep submicron CMOS, design of a high DC-gain opamp for the MDAC is a serious obstacle due to reduced intrinsic transistor gain and sub-1V supply voltage. Hence, all designs utilize digital calibration to counter gain error and tolerate the use of a low-gain amplifier. Calibration times of at least several tens of ms are required, resulting in lengthy start-up times and reduced SoC power efficiency. Moreover, such calibration cannot track sudden supply voltage variations and suppressing such fluctuations with bypass capacitors significantly impacts chip cost [1–2]. Furthermore, amplifier non-linearity remains unsolved; with lower supply voltages, the limited amplifier swing tightens SAR noise requirements.

Passive Noise Shaping in SAR ADC With Improved Efficiency

Abstract: This brief reports a passive noise-shaping (PNS) scheme for successive approximation register (SAR) analog-to-digital converter (ADC) based on the two-step integration with passive gain and comparator gain techniques. The analysis shows that the proposed method achieves a better noise-shaping (NS) efficiency than prior arts, which enhances the noise attenuation by 14 dB. A design example is provided which further adopts the delta-sampling technique to relieve the conversion efficiency loss due to the oversampling in the NS SAR ADC. The efficiency of the proposed PNS scheme and the performance of the ADC are verified by simulation achieving a 13.2 effective number of bits with a 10-b ADC architecture and eight conversion cycles for a signal bandwidth of 2 MHz sampled at 100 MS/s. The calculated Schreier figure of merit (FoM) and Walden FoM are 176.8 dB and 16 fJ/conv.-step, respectively.

A Low-Power High-Speed Hybrid ADC With Merged Sample-and-Hold and DAC Functions for Efficient Subranging Time-Interleaved Operation

Abstract: An 8-bit 1-GS/s hybrid analog-to-digital converter (ADC) for high-speed low-power applications is introduced. It has a subranging architecture with a 3-bit flash ADC as a first stage and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. In each channel, a merged sample-and-hold and capacitive digital-to-analog converter (SHDAC) performs the sampling and residue generation for the subranging operation. The effects of the parasitic capacitances on the SHDAC linearity are analyzed, and a linearity correction method is introduced to enable power-efficient high-speed operation in the presence of parasitics because the design approach allows reducing the sampling capacitance in the SHDAC. Furthermore, the sampling network configuration incorporates an error reduction technique to alleviate the clock feedthrough of bootstrap switches. The offsets of the comparators in the flash ADC are calibrated using a built-in reference signal via an extra sampling channel. According to postlayout simulations at 1 GS/s in 130-nm CMOS, the ADC has an effective number of bits higher than 7.37 bits up to the Nyquist frequency while consuming 13.3 mW from a 1.2-V supply.

Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC

Abstract: This paper proposes a linearity calibration algorithm of a capacitive digital-to-analog converter (CDAC) for successive approximation register (SAR) analog-to-digital converters (ADCs) based on a normalized-full-scale of the DAC. Since the capacitor weight errors are represented as the difference between the real and ideal weights with respect to the normalized-full-scale, the calibrated digital representation of CDAC does not have gain error. A model of a 14-bit-format SAR ADC with a segmented CDAC by a bridge capacitor is simulated to demonstrate the performance of the proposed calibration algorithm. The effective number of bits (ENOB) and spurious-free dynamic range (SFDR) of the 14-bit-format ADC model are improved to 13.2 bits and 94.0 dB from 8.4 bits and 54.8 dB, respectively, at a standard deviation of a unit capacitor of 2%. The gain-error-free characteristic of the proposed linearity calibration algorithm is verified with a 2-channel time-interleaved (TI) SAR ADC model.

An 11.0 bit ENOB, 9.8 fJ/conv.-step noise-shaping SAR ADC calibrated by least squares estimation

Abstract: A noise-shaping SAR ADC implemented in 28 nm UTBB FDSOI is presented. A cascaded FIR-IIR loop filter topology is used, and implemented as an inverter-based switched-capacitor circuit. The loop filter also employs input buffers. To correct CDAC mismatch, an off-line calibration technique that estimates the CDAC calibration coefficients from a digitized test sequence is proposed and used. At 28 MS/s and Nyquist bandwidth of 1.75 MHz, the measured accuracy is 11.0 bit ENOB, and the Walden FOM 9.8 fJ/conv.-step.

A Power-Efficient Signal-Specific ADC for Sensor-Interface Applications

Abstract: A novel signal-specific power-efficient analog-to-digital converter (ADC) is proposed for sensor-interface applications Instead of digitizing each analog sample independently, the proposed ADC determines the digital code corresponding to each new input sample by digitizing the difference of two consecutive samples Therefore, for the applications with low-varying input signals, such as image sensors and ECG readouts, the difference of two consecutive samples is much smaller than the ADC full-scale range for the majority of the input samples, the power consumption of the capacitive digital-to-analog converter, the comparator, and the digital circuits of the proposed ADC is saved due to reducing the ADC activity The prototype was fabricated using a 018- ${\mu }\text{m}$ CMOS technology Measurement results of 1 V, 8 bit, 20 kS/s ADC confirm that for a 10-kHz input sine wave, the effective number of bits is 7 while the power consumption of the entire ADC is 112 $ {\mu }\text{W}$ However, for the same sampling rate, the power consumption is only 106 nW for a low-varying 100-Hz input sine wave

13.10 A >1W 2.2GHz switched-capacitor digital power amplifier with wideband mixed-domain multi-tap FIR filtering of OOB noise floor

Abstract: Digital power amplifiers and transmitters have drawn significant interest in the recent past due to their reconfigurability, compatibility with CMOS technology scaling and DSP, and potential for automated design synthesis [1–5]. While significant progress has been made in achieving moderate output power levels in CMOS, wideband modulation, and high efficiency under back-off, out-of-band emissions remain an unsolved problem. The elimination of the analog reconstruction filter that follows the DAC in a conventional analog transmitter implies that broadband DAC quantization noise appears at the output of the transmitter unfiltered. Quantization noise can be suppressed by increasing resolution and/or sampling rate, but to meet the challenging −150 to −160dBc/Hz out-of-band (OOB and specifically RX-band) noise requirement of FDD with conventional duplexers, nearly 12b at 0.5GS/s is required. Such a high effective number of bits (ENOB) is extremely challenging in digital PAs given their strong output nonlinearity. Consequently, while low-power modulators are able to approach −150dBc/Hz RX-band noise floor and below [6], state-of-the-art digital transmitters achieve −130 to −135dBc/Hz RX-band noise, nearly 20dB or 100× away [2–4]. Embedding mixed-domain FIR filtering into digital transmitters to create notches in the RX band has been proposed [4,7], but, while successful in low-power modulators [7], nonlinearity significantly limits notch depth to <10dB in digital PAs [4]. Further, notch bandwidth (BW) is far less than 20MHz, the typical LTE BW, in the simple two-tap FIR structures that have been explored [4].

A 43.6-dB SNDR 1-GS/s single-channel SAR ADC using coarse and fine comparators with background comparator offset calibration

Abstract: A 43.6dB-SNDR 1-GS/s 8-bit single-channel successive-approximation-register (SAR) analog-to-digital converter (ADC) using coarse and fine comparators with fully background comparator offset calibration is presented. Low-power coarse comparators and low-noise fine comparators are both employed to improve the comparator power efficiency. Non-binary digital-to-analog converter (DAC) with redundancy is employed to tolerate possible errors in the most-significant-bit (MSB) decisions. A novel comparator offset calibration scheme is proposed to remove the offsets between the different comparators, without slowing down the speed of the SAR conversion. The prototype ADC is implemented in a 28 nm CMOS technology and achieves an ENOB of 6.95 (43.6-dB SNDR) near Nyquist frequency while consuming 3.2 mW, translating into an FOM of 25.87 fJ/conversion-step. To the best of our knowledge, this ADC achieved the highest SNDR among all single-channel SAR ADCs reported that operate above 1GS/s.

Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing

Abstract: This paper proposes the different way of designing standard-cell based flash ADC in order to increase its input dynamic range. It includes implementation of 5-bit flash ADC for fully automated digital synthesis. The input dynamic range is increased by including 5-input logic gates. The proposed architecture results in Differential Non-Linearity (DNL) of ±0.206 LSB and Integral Non-Linearity (INL) of ± 0.218 LSB range. This standard-cell based flash ADC has Effective Number of Bits (ENOB) of 4.78 bits at the sampling frequency of 400 MS/s. The Spurious-Free Dynamic Range (SFDR) of 42.05 dB is achieved at an input frequency of 1.95 MHz.

High Temperature Data Converters in Silicon Carbide CMOS

Abstract: This paper presents an 8-b digital to analog converter (DAC) and 8-b analog to digital converter (ADC) for high-temperature applications. The pair of data converters were designed in a 1.2- $\mu \text{m}$ silicon carbide CMOS process and have been tested from 25 °C to 400 °C. At 400 °C, the DAC has a maximum differential nonlinearity (DNL) and integral nonlinearity (INL) error of 1.2 least significant bit (LSB) and 2.7 LSB, respectively, while the offset and the gain error are 5.9 and 2.7 LSB. The ADC has a maximum DNL and INL error of 3.6 and −3 LSB, respectively, while the offset error is −7 LSB and the gain error is 2.6 LSB. The ADC has an SNDR = 32.15 dB and effective number of bits = 5.05 b at 300 °C. The DAC is the first of its kind in silicon carbide CMOS, while the ADC is the first reported at temperatures over 300 °C.

An 11-bit 100-MS/s Subranged-SAR ADC in 65-nm CMOS

Abstract: This paper presents an 11-bit successive approximation register (SAR) analog-to-digital converter (ADC). The subranged-SAR ADC architecture is applied to achieve a sampling rate of 100 MHz. The proposed gain error compensation helps attenuate the gain error between coarse and fine ADCs. An up-then-down digital-to-analog converter (DAC) switching scheme is used to maintain a small common-mode variation for the fine comparator. To maintain a good spurious free dynamic range (SFDR), the capacitor-swapping scheme is applied in the DAC. The prototype ADC was implemented using a 65-nm CMOS technology. It consumes a total power of 2.4 mW from a 1.2-V supply. The measured peak signal-to-noise-and-distortion ratio and SFDR are 61.1 and 85 dB, respectively. The peak effective number of bits is 9.86, equivalent to a figure-of-merit of 25.8 fJ/conversion step.

A 40 GS/s 4 bit SiGe BiCMOS flash ADC

Abstract: This paper presents the design and experimental test of a 40 GS/s 4 bit single-core flash ADC in a 0.13 μm SiGe BiCMOS technology. The ADC exploits a traveling-wave concept and integrates a new low-complexity Pseudo-XOR gray encoder that makes use of folded-cascode differential logic. Up to a sampling rate of 39.04 GS/s the ADC provides a measured ENOB of more than 3 bits and a SFDR of more than 24.8 dBc within the frequency band from DC to 20 GHz. At 40.32 GS/s the frequency band for a minimum effective resolution of 3 bits is 12 GHz and at 42.24 GS/s it is about 5.3 GHz.

A Fully Digital Background Calibration Technique for M-Channel Time-Interleaved ADCs

Abstract: In this paper, we propose a pure digital blind calibration method to estimate and calibrate offset, gain and timing mismatches. Gain errors are calibrated based on first channel correction using an overall reference, whereas for the rest of the $$(M-1)$$ channels, the corrected first channel becomes the reference channel. Time skew calibration is performed using a derivative filter followed by a fractional delay filter and a scaling factor. The proposed technique significantly reduces the required hardware resources, specifically for the derivative and fractional delay filters for which no look-up table is required. In addition, the proposed method requires only two finite impulse response filters with fixed coefficients, thus reducing complexity and hardware resources, as compared to adaptive filter techniques. For a sampling frequency of 3.072 GHz, the maximum achievable signal-to-noise and distortion ratio is 67 dB, resulting in effective number of bits of 10.83 for a 12-bit resolution analog-to-digital converter.

A high-precision CMOS biophotometry sensor with noise cancellation and two-step A/D conversion

Abstract: Fluorescence biophotometry measurements require wide dynamic range (DR) and high sensitivity laboratory apparatus. Indeed, it is often very challenging to accurately resolve the small fluorescence variations in presence of high background tissue autofluorescence. There is a great need for smaller detectors combining high linearity, high sensitivity, and high-energy efficiency. This paper presents a new high-dynamic range CMOS photodetector embedding a photosensor and a high-precision two-step analog-to-digital converter (ADC) with a noise cancellation scheme. In this system, a 16-bit two-step ADC sucessivley uses an integrating ADC and a successive approximation register (SAR) ADC enabling wide dynamic range and high energy-efficiency photocurrent quantization. Noise cancellation is achieved through a SAR digital-to-analog (DAC) capacitor bank to store and subtract the low-frequency noise from the output of a capacitive transimpedance amplifier (CTIA) throughout each data conversion. The 6-most significant bits are resolved through the integrating ADC, while the 10-least significant bits are extracted by the SAR ADC. The two-step data converter uses a hardware sharing scheme to decrease the chip size and to improve energy-efficiency. The proposed optoelectronic detector is implemented in a 0.18-µm CMOS technology, consuming 60 µW from a 3.3-V supply voltage while achieving a DR of 94 dB, a minimum detectable current of 200-ƒA rms , at 1-kS/s sampling rate. The proposed biosensor presents a FOM of 1.46 pJ/conv. which is among the best reported performance among similar systems.