Showing papers on "Effective number of bits published in 2018"

A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure

Abstract: The noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) is an emerging hybrid architecture that achieves high resolution and power efficiency simultaneously by combining the merits of the SAR ADC and the $\Delta \Sigma $ ADC. Most prior works adopting the cascaded integrator feed-forward (CIFF) structure demonstrate inefficiency in realizing optimized noise transfer function (NTF). This paper presents a second-order NS-SAR ADC employing the error-feedback (EF) structure to realize complex NTF zeros for noise-shaping enhancement with the minimum modification to a standard SAR. It implements a low-power scaling-friendly EF path by using a passive finite impulse response (FIR) and a comparator-reused dynamic amplifier with process-voltage-temperature (PVT) tracking background calibration. Fabricated in 40-nm CMOS, the prototype chip consumes $84~\mu \text{W}$ when operating at 10 MS/s. The NS-SAR achieves peak Schreier FoM of 178 dB with 79-dB signal to noise and distortion ratio (SNDR) at an oversampling ratio (OSR) of 8.

A Reconfigurable 10-to-12-b 80-to-20-MS/s Bandwidth Scalable SAR ADC

Abstract: An asynchronous successive approximation register analog-to-digital converter (ADC) for wideband multi-standard systems is presented. The ADC can be configured as an 80-MS/s 10-b, 40-MS/s 11-b, or 20-MS/s 12-b converter. Time-interleaved technique is applied to expand sampling bandwidth exponentially while resolution scales down. The channel mismatches are cancelled by the digital calibration technique. The bulk-biasing technique is used in the sampling switch to reduce the influence of the charge injection caused by the top-plate sampling. In addition, the configurable asynchronous processing is employed to extend the flexibility of speed and resolution tradeoff. Moreover, the two-step digital-to-analog converter (DAC) switching method is proposed to reduce the switching energy of the DAC. Prototyped in 180-nm CMOS process, the ADC achieves the 56.7-/61.2-/64.6-dB signal-to-noise and distortion ratio (SNDR) and 72.3-/74.8-/75.5-dB spurious-free dynamic range (SFDR) at 80-/40-/20-MHz sampling frequency with the power consumption of 2.61/2.05/1.77 mW.

A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation

Abstract: This paper demonstrates a multi-bit/cycle successive-approximation register (SAR) analog-to-digital converter (ADC) architecture for low-power and high-speed operation. The proposed dual reference shifting and interpolation technique reduces the power and area overhead of the multi-bit/ cycle SAR architecture, allowing for a higher number of bit quantization for each conversion cycle and thus, a higher conversion rate. To prove the concept, a 12-bit 32-way time-interleaved 4-b/cycle SAR ADC prototype is fabricated in 65-nm CMOS technology. The ADC prototype can be configured with multiple sampling rates (1.6, 3.2, and 6.4 GS/s). It measures a peak effective number of bits (ENOB) of 10.9 bits at 6.4 GS/s and 9.4 ENOB at the maximum input frequency of 1 GHz. The prototype achieves a Schreier figure-of-merit (FOMSchreier) of 154.9 dB at 6.4-GS/s sampling rate.

Breaking Through the Speed-Power-Accuracy Tradeoff in ADCs Using a Memristive Neuromorphic Architecture

Abstract: The analog-to-digital converter (ADC) is a principal component in every data acquisition system. Unfortunately, modern ADCs tradeoff speed, power, and accuracy. In this paper, novel neuroinspired approaches are used to design a smart ADC that could be trained in real time for general purpose applications and break through conventional ADC limitations. Motivated by artificial intelligent learning algorithms and neural network architectures, the proposed ADC integrates emerging memristor technology with CMOS. We design a trainable four-bit ADC with a memristive neural network that implements the online gradient descent algorithm. This supervised machine learning algorithm fits multiple application specifications such as full-scale voltage ranges and sampling frequencies. Theoretical analysis, as well as simulation results, demonstrate highly powerful collective properties, including reconfiguration, mismatch self-calibration, adaptation to dynamic voltage and frequency scaling, noise tolerance, and power consumption optimization. The proposed ADC achieves 8.25 fJ/conv FOM, 3.7 ENOB, 0.4 LSB INL, and 0.5 LSB DNL. These promising properties make it a leading contender for general purpose and emerging data driven applications.

A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization

Abstract: A two-time interleaved pipelined SAR ADC in 16-nm CMOS achieving 11.2-bit ENOB at 300 MS/s is presented. To cancel the signal-dependent voltage ripple on the reference node due to DAC switching, it employs a stabilization scheme based on the use of auxiliary DACs. The charge drawn from the reference becomes signal-independent, greatly reducing the requirements for the reference decoupling capacitance and/or buffers. The technique improves the linearity to levels better than 76-dB harmonic distortion. Power consumption is only 3.6 mW resulting in peak FoMs of 175.5 dB and 5.1 fJ/conv.step.

A 15.2-ENOB 5-kHz BW 4.5- $\mu$ W Chopped CT $\Delta\Sigma$ -ADC for Artifact-Tolerant Neural Recording Front Ends

Abstract: Implantable closed-loop neural stimulation is desirable for clinical translation and basic neuroscience research. Neural stimulation generates large artifacts at the recording sites, which saturate existing recording front ends. This paper presents a low-power continuous-time delta-sigma analog to digital converter (ADC), which along with an 8 $\times $ gain capacitively-coupled chopper instrumentation amplifier (CCIA), realizes a front end that can digitize neural signals from 1 Hz to 5 kHz in the presence of 200-mVpp differential artifacts and 700-mVpp common-mode (CM) artifacts. A modified loop-filter is used in the ADC along with new linearization techniques to significantly reduce power consumption. Fabricated in 40-nm CMOS, the ADC occupies an area of 0.053 mm2, consumes 4.5 $\mu \text{W}$ from a 1.2-V supply, has an input impedance of 20 $\text{M}\Omega $ and bandwidth (BW) of 5 kHz, and achieves a peak signal to noise and distortion ratio (SNDR) of 93.5 dB for a 1.77- $\text{V}_{\mathrm {pp}}$ differential input at 1 kHz. The ADC’s figure of merit (FOM) (using SNDR) is 184 dB, which is 6 dB higher than the state of the art in high-resolution ADCs. The complete front end occupies an area of 0.113 mm2, consumes 7.3 $\mu \text{W}$ from a 1.2-V supply, has a dc input impedance of 1.5 $\text{G}\Omega $ , input-referred noise of 6.35 $\mu \text{V}_{\mathrm {rms}}$ in 1 Hz–5 kHz, and total harmonic distortion of −81 dB for a 200-mVpp input at 1 kHz, and is immune to 700-mVpp CM interference. Compared to front ends intended for closed-loop neural recording, this paper improves the linear input range by 2 $\times $ , the signal BW by 10 $\times $ , the dynamic range by 12.6 dB, the FOM by 12.4 dB and remains immune to large CM interference while maintaining comparable power, area, and noise performance.

A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting DAC

Abstract: This paper presents an 11-bit ultralow voltage energy efficient successive approximation register (SAR) analog-to-digital converter (ADC). With the proposed semi-resting (SR) digital-to-analog convertor (DAC) switching scheme, this paper consumes only 6%–13.5% switching energy, compared to the state-of-the-art works. In addition, the SR switching scheme effectively reduces the differential nonlinearity and integral nonlinearity to be 1/2, compared to the conventional approach under the same matching conditions. With the proposed SR DAC switching scheme, this paper can handle the same input swing using a half supply and consume smaller power consumption. A cascade-input comparator is developed to consume only 49% of the power and 66% of the decision time with a threefold front-stage gain boost. The test chip occupies a core area of 0.035 mm2 in 90-nm CMOS technology. The prototype consumes 187 nW at 600 kS/s with a single 0.3-V supply voltage. The achieved effective number of bits and spurious-free dynamic range at Nyquist input are 9.46 bits and 73 dB, respectively. The resultant Walden’s figure of merit (FoM) and Schreier’s FoM are 0.44 fJ/conversion-step and 180.8 dB, respectively.

An Energy-Efficient DAC Switching Method for SAR ADCs

Abstract: This brief presents a capacitor switching technique to reduce the power consumption in successive approximation register (SAR) analog-to-digital converters (ADCs). The proposed method ideally does not consume any switching energy in digital-to-analog converter and for a 10-bit ADC; it achieves 87% reduction in the total capacitor area compared to the conventional SAR ADC. In addition, the accuracy of the proposed SAR ADC does not depend on the accuracy of the mid-level reference voltage ( $ {V}_{\text{cm}}$ ). Moreover, the common-mode input voltage of the comparator will remain constant. The proposed ADC is simulated in a 90-nm CMOS technology with sampling rate of 100 kS/s and resolution of 10-bit. The simulation results achieve an 8.5 effective number of bits with about 0.5- ${\mu }\text{W}$ power consumption resulting in a FoM of 9.76 fJ/conversion-step.

Frequency Dependent ENoB Requirements for M-QAM Optical Links: An Analysis Using an Improved Digital to Analog Converter Model

Abstract: Digital-to-Analog Converters (DACs) are a key technology for high-speed optical links and are widely deployed. A new and improved model for a DAC that accurately accounts for the frequency dependent nature of ENoB and is computationally efficient is validated through both simulations and experiments. Furthermore, the impact of the various model parameters such as quantization, timing jitter and bandwidth, on the performance of 16QAM, 64QAM, and 256QAM are presented.

A Bypass-Switching SAR ADC With a Dynamic Proximity Comparator for Biomedical Applications

Abstract: A bypass-switching successive approximation (BSSA) register analog-to-digital converter (ADC) employing a newly proposed dynamic proximity comparator is presented in this paper. By exploiting the current characteristics of a current correlator, the proposed comparator generates the bypass signal directly along with the polarity comparison result. The bypass window size can be adjusted to optimize the power reduction for different sensing applications with low-voltage sensitivity. A BSSA logic circuit is adopted with reduced number of logic gates as well as switching power. A prototyped chip including a proposed ADC has been designed and fabricated in a 0.18- $\mu \text{m}$ CMOS process occupying an area of 0.041 mm2. With a supply voltage of 0.6 V and at a sampling rate of 50 kS/s, the measured signal-to-noise-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 56.9 and 68.7 dB, respectively, achieving an effective number of bits (ENoB) of 9.16. The ADC consumes power of 114 nW while digitizing sinusoidal inputs. With a bypass window size of ±32 LSBs, the designed ADC consumes only 76 nW when quantizing full-scale electrocardiography signals that are generated from a certified commercial simulator, exhibiting a figure-of-merit (FoM) of 2.66 fJ/conversion-step. Besides ECG signals, the ADC is also demonstrated by digitizing electromyography and electrooculography signals from human bodies.

A 0.5-V 12-bit SAR ADC Using Adaptive Time-Domain Comparator With Noise Optimization

Abstract: This paper presents a 05-V 12-bit low-voltage power-efficient successive-approximation register (SAR) analog-to-digital converter (ADC) using an adaptive time-domain (ATD) comparator with noise optimization To be power efficient with different residual input levels ( $\Delta V_{\mathrm {in}}$ ) during conversion, the proposed ATD comparator automatically adjusts its input-referred noise performance rather than consuming the same power for each bit conversion Considering the noise requirement of 12-bit resolution, the proposed ATD technique effectively reduces the comparator power consumption by 50% compared to the conventional approach Moreover, a differential threshold window (DTW) technique is also developed to provide the optimized time-domain threshold for lowest figure-of-merit (FoM) performance with a self-adjusted ( $V_{\mathrm {ctrlp}}$ – $V_{\mathrm {ctrln}}$ ), depending on process–voltage–temperature (PVT) variation The test chip occupies a core area of 0109 mm2 in Taiwan Semiconductor Manufacturing Company (TSMC) 90-nm CMOS technology With a 05-V supply voltage, the prototype consumes 810 and 1425 nW at 100 and 250 kS/s, respectively The achieved effective number of bits and signal-to-noise and distortion ratio with Nyquist-rate input are 1071/103 bit and 663/638 dB, respectively The resultant Walden FoM and Schreier FoM are 482/452 fJ/conversion step and 1742/17323 dB, respectively

A 0.2-V 30-MS/s 11b-ENOB Open-Loop VCO-Based ADC in 28-nm CMOS

Abstract: We present a 0.2-V open-loop voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) intended for IoT wireless sensor nodes. A resistor-based frequency-tuning scheme helps in mitigating odd-order harmonic distortion induced by the VCO nonlinear transfer characteristic. It also provides a reconfigurable input range, allowing it to exceed the supply by $2.5{\times }$ (single-ended), and maintaining tolerance against ±10% supply variations. Latch, flip-flops, and logic gates within the frequency-to-digital converter are designed for minimum propagation delays, allowing sampling at 30 MS/s. The ADC is implemented in 28-nm CMOS and achieves a peak SNDR of 68 dB, equivalent to an ENOB of 11, over a 61-kHz bandwidth with a 1- $\text{V}_{\mathrm{pp}}$ input differential sinewave. It consumes 7 ${\mu }\text{W}$ , resulting in a state-of-the-art Walden and Schreier FoM of 27.8 fJ/c-s and 167.4 dB, respectively.

A 13-ENOB 2 nd -order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure

Abstract: The noise-shaping (NS) SAR ADC is an emerging hybrid architecture that achieves high resolution and power-efficiency simultaneously by combining the merits of the SAR ADC and the AIADC, making it attractive to sensor readout and healthcare applications. To implement NS, most prior works adopted the classic cascaded integrator feed-forward (CIFF) structure for noise filtering [1-5]. Opamp-based integrators were used in [1-3] to achieve a relatively sharp noise transfer function (NTF), but at the cost of power and scaling friendliness. Reference [4] demonstrated 2nd-order NS using fully passive switched-capacitor (SC) integrators, but has limited NS and thermal noise performance. Reference [5] combines passive SC filters with a dynamic amplifier (D-amp) to achieve good noise and power, but is vulnerable to process-voltage-temperature (PVT) variations. In addition, no prior NS SAR has realized complex NTF zeros for optimum NS. This presents a need for an NS SAR ADC that can combine optimized NTF, power efficiency and PVT robustness. To overcome the limitations of existing work, instead of adopting the CIFF structure, this paper presents a 2nd-order NS SAR ADC using an error-feedback (EF) structure. It highlights the capability of realizing optimized complex NTF zeros by simply using charge sharing summation, a passive SC FIR and a comparator-reused dynamic amplifier with PVT tracking. This work achieves sharp NS performance while maintaining both hardware and power efficiency merits of the NS SAR with improved robustness. The prototype chip, fabricated in 40nm CMOS, achieves a 79dB SNDR at an OSR of 8 using a 9b SAR, resulting in a peak Schreier FoM of 178dB.

A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET

Abstract: Optical communication standards, such as ITU OTU-4, OIF 112G and 100/400Gb/s Ethernet, require ADCs with more than 50GS/s and at least 5 ENOB to enable complex digital equalization, and a growing number of appropriate designs have been presented [1-4], mostly time-interleaved SAR ADCs. Most of these ADCs were not intended for input frequencies up to Nyquist and report an input range up to approximately 20GHz, often equivalent to the analog 3dB bandwidth. Ultimately, the analog bandwidth is less relevant than SNDR at high frequencies because an FIR filter can equalize amplitude degradation, but not increase SNDR. The design presented in this paper does not focus on the 3dB bandwidth, but it is optimized for best SNDR at the Nyquist frequency of up to 36GHz. Low power and area are critical for many applications and are achieved by an optimized SAR that allows low supply voltages while still maintaining high speed and accuracy. At 72GS/s, the ADC achieves 39.3dB at low input frequencies and 30.4dB at Nyquist. It consumes 235mW at 72GS/s and 97mW at 48GS/s, which results in 3.3pJ and 2.0pJ per conversion, respectively. The ADC is implemented in an area of 0.15mm2 in 14nm CMOS FinFET technology.

A 0.13- $\mu\text{m}$ CMOS SoC for Simultaneous Multichannel Optogenetics and Neural Recording

Abstract: This paper presents a 0.13- $\mu \text{m}$ CMOS system-on-chip (SoC) for simultaneous multichannel optogenetics and multichannel neural recording in freely moving laboratory animals. This fully integrated system provides 10 multimodal recording channels with analog-to-digital conversion and a four- channel LED driver circuit for optogenetic stimulation. The bio-amplifier design includes a programmable bandwidth (BW) (0.5 Hz–7 kHz) to collect either the action potentials (APs) and/or the local field potentials (LFPs) and has a noise efficiency factor (NEF) of 2.30 for an input-referred noise of 3.2 $\mu V_{\text {rms}}$ within a BW of 10–7 kHz. The low-power delta–sigma ( $\Delta \Sigma $ ) MASH 1-1-1 analog-to-digital converter (ADC) is designed to work at low oversampling ratios (OSRs) (≤50) and has an effective number of bits (ENOB) of 9.75 bits at an OSR of 25 (BW of 10 kHz). The utilization of a $\Delta \Sigma $ ADC is the key to address the flexibility needed to address different noise versus power consumption tradeoff of various experimental settings. It leverages a new technique that reduces its size by subtracting the output of each $\Delta \Sigma $ branch in the digital domain, instead of in the analog domain as done conventionally. The ADC is followed by an on-chip fourth-order cascaded integrator-comb (CIC4) decimation filter (DF). A whole recording channel, including the bio-amplifier, the $\Delta \Sigma $ MASH 1-1-1, and the DF consumes 11.2 $\mu \text{W}$ . Optical stimulation is performed with an LED driver using a regulated cascode current source with feedback that can accommodate a wide range of LED parameters and battery voltages. The SoC is validated in vivo within a wireless experimental platform in both the ventral posteromedial nucleus (VPM) and cerebral motor cortex brain regions of a virally mediated Channelrhodopsin-2 (ChR2) rat.

DIDACTIC: A Data-Intelligent Digital-to-Analog Converter with a Trainable Integrated Circuit using Memristors

Abstract: In an increasingly data-diverse world, in which data are interactively transferred at high rates, there is an ever-growing demand for high-precision data converters. In this paper, we propose a novel digital-to-analog converter (DAC) configuration that is calibrated using an artificial intelligence neural network technique. The proposed technique is demonstrated on an adaptive and self-calibrated binary-weighted DAC that can be configured on-chip in real time. We design a reconfigurable 4-bit DAC with a memristor-based neural network. This circuit uses an online supervised machine learning algorithm called “binary-weighted time-varying gradient descent.” This algorithm fits multiple full-scale voltage ranges and sampling frequencies by iterative synaptic adjustments, while inherently providing mismatch calibration and noise tolerance. Theoretical analysis, as well as simulation results, show the efficiency and robustness of the training algorithm in reconfiguration, self-calibration, and desensitization, leading to a significant improvement in DAC accuracy: 0.12 LSB in terms of integral non-linearity, 0.11 LSB in terms of differential non-linearity, and 3.63 bits in terms of effective number of bits. The findings constitute a promising milestone toward scalable data-driven converters using deep neural networks.

Experimental Study on a 4-b Serial Optical Digital to Analog Convertor

Abstract: Photonic techniques have potential to overcome the limitations of electronic digital-to-analog conversion. A serial optical DAC, using fiber dispersion with optical weighted wavelength multiplexing, is proposed and demonstrated. Serial Digital codes are overlapped regularly in time domain due to dispersion-based delays. Intensity information for the conversion is extracted by synchronous gating pulse train. The system is operated with a high precision time control. Performance of the ODAC is experimentally investigated by establishing a 4-b 12.5 Gb/s system. The linear transfer function is described and an ENOB of 3.55 is obtained. The proposed architecture could be easily modified for better performance.

A Current-Mode Capacitively-Coupled Chopper Instrumentation Amplifier for Biopotential Recording With Resistive or Capacitive Electrodes

Abstract: This brief presents a high-density, low-noise analog front-end (AFE) for capacitively coupled neural recording applications. Conventional capacitively coupled AFEs, when chopper-stabilized, require large coupling capacitors or servo loops to minimize $ {1/f^{2}}$ input-referred noise and chopper-induced offsets, limiting channel density. In this brief, a current-mode capacitively coupled chopper instrumentation amplifier with embedded delta-sigma analog-to-digital converter (ADC) is presented that enables an area-efficient low-noise design via chopper-stabilized current-mode amplification. In this design, 60 channels are implemented in a $ {2 \times 2}$ mm2 180-nm CMOS chip, and each channel consumes $4~ {\mu }\text{W}$ , achieves an input referred noise of 160 nV/ $\sqrt {\text{Hz}}$ , and an ADC effective number of bits of 8.5 bits.

A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching Scheme

Abstract: This paper presents a 12-bit 40-MS/s successive approximation register analog-to-digital converter (ADC) for ultrasound imaging systems. By incorporating a fast binary window digital-to-analog converter (DAC) switching technique, the problematic most significant bit transition glitch was removed to improve linearity without increasing the input capacitance or using a calibration scheme. A hybrid DAC was also developed to overcome the yield problem that occurs when a tiny unit capacitance is used in the DAC. Moreover, a reference buffer was used to accelerate the DAC settling to achieve high-speed conversion. The prototype ADC was fabricated using a 130-nm CMOS technology. The ADC core occupied an active area of 0.1 mm2 and consumed a total power of 1.32 mW when a 1.2-V supply was used at a conversion rate of 40 MS/s. The measured peak signal-to-noise-and-distortion ratio and spurious-free dynamic range were 64 and 77.5 dB, respectively. The peak effective number of bits was 10.33, which is equivalent to a Walden figure-of-merit of 25.6 fJ/conversion step.

A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling

Abstract: This paper introduces a high-order continuous-time (CT) delta-sigma modulator (DSM) that applies digital-domain noise coupling (DNC) based on the structural advantages of the successive-approximation register (SAR) analog-to-digital converter (ADC), which makes the implementation of second-order noise coupling very simple. Due to digital-domain implementation as well as the SAR ADC where the key building blocks are embedded for the proposed DNC, compact size and efficient power consumption could be designed. For low circuit noise, a feedback DAC is implemented with a tri-level current-steering DAC. Tri-level data-weight averaging (TDWA) improves the linearity of the DAC. With the proposed DNC and TDWA, a prototype CT DSM fabricated in a 28-nm CMOS achieves a peak 74.4-dB SNDR and an 80.8-dB dynamic range (DR) for a 10-MHz BW with an oversampling ratio of 16, resulting in a Schreier FoMDR of 174.5 dB. The chip area occupies 0.1 mm2, and the power consumption is 4.2 mW.

A 38-mW 7-bit 5-GS/s Time-Interleaved SAR ADC with Background Skew Calibration

Abstract: This paper presents a 7-bit 5-GS/s time-interleaved SAR ADC with background timing skew calibration. The two-step approaching skew calibration was proposed to reduce the tuning range of the digital control delay circuit, thus suppress the additional clock jitter. The ping-pong domino-SAR ADC architecture was proposed to speed up channel-ADCs. The prototype ADC consumes a total power of 38 mW from a 1.2V supply and occupies an active area of 0.69 mm2 in a 55 nm low-power CMOS technology. For 10 MHz input, the measured SNDR and SFDR are 42.7 and 65 dB, respectively. The ENOB is 6.8 bits, equivalent to the peak FOM of 69 fJ/conversion-step. At the Nyquist rate, this ADC achieves 35.9 dB SNDR and 45 dB SFDR The ENOB is 5.7 bits, equivalent to the Nyquist FOM of 150 fJ/conversion-step.

A 1.8 V 3 GS/s 7-bit time-interleaved Quasi C-2C SAR ADC using voltage-comparator time-information

Abstract: This paper presents a 7-bit 15 × interleaved SAR ADC that operates up to 3 GS/s, using 180 nm CMOS technology. The ADC utilizes the transient information of a dynamic SAR voltage-comparator to resolve 2 bits per clock cycle, using a time-comparator block. Thus, only 5 clock cycles are needed to resolve 7 bits. This results in speed improvement of about 60%, compared to conventional ADC. Also, an improved Quasi C-2 C DAC structure with reduced internal node swing and reduced switching activity are utilized, which decreases the power consumption of DAC up to 65%. We employ the above techniques in designing a 7-bit SAR ADC, in which 3 bits are resolved with time-comparator blocks and 4 bits are resolved with a voltage-comparator. To calibrate the proposed time-comparator block, a calibration process is proposed. ADS simulation of the ADC illustrates an ENOB (Effective Number of Bits) > 6.5-bit and SFDR (Spur Free Dynamic Range) = −52.8 dBc for a single SAR converter with sampling at 200 MS/s. For the time-interleaved SAR ADC with 15 single SAR converters, ENOB is 6.15-bit and SFDR = −45 dBc with sampling at 3 GS/s up to Nyquist frequency. This ADC consumes 150 mW at 1.8 V supply and achieves a Figure-of-Merit (FoM) of 700 fJ/conv-step.

A Wirelessly Powered UWB RFID Sensor Tag With Time-Domain Analog-to-Information Interface

Abstract: This paper presents a wirelessly powered radio frequency identification sensor tag with an analog-to-information interface. A time-domain interface, incorporating an ultra-low-power impulse radio ultra-wideband (IR-UWB) transmitter (TX), is employed. The analog signal from the sensor is compared with a triangular waveform, resulting in a pulse-position modulation signal to trigger UWB pulses. Thanks to the high time-resolution IR-UWB radio, time intervals of the impulses can be used to represent the original input value, which is measured remotely on the reader side by a time-of-arrival estimator. This approach not only eliminates the analog-to-digital converter (ADC) but also significantly reduces the number of bits to be transmitted for power saving. The proposed tag is fabricated in a 0.18- $\mu \text{m}$ CMOS process with an active area of 2.5 mm2. The measurement results demonstrate that a 300-kS/s sampling rate with a 6.7-bit effective number of bits (ENOB) is obtained via a UWB receiver with a sensitivity of −93 dBm and an integration window of 10 ns. The ENOB is improved to 7.3 bits when the integration window is reduced to 2 ns. The tag can be powered up by a −18-dBm UHF input signal. The power consumption of the proposed tag is 41.5 $\mu \text{W}$ yielding a 1.3-pJ/conv.step figure of merit, offering 9 $\times $ and 67 $\times $ improvements compared with the state of the art based on an ADC and a backscattering TX, and the tag based on an ADC and a narrowband TX, respectively.

Artifact-Tolerant Opamp-Less Delta-Modulated Bidirectional Neuro-Interface

Abstract: We present a 16-channel bidirectional wireless neural interface with arbitrary-waveform neurostimulators triggered by remote closed-loop analysis of simultaneously recorded neural activity. The delta-modulated neural ADC uses no input capacitors and no statically-biased circuits such as opamps, saving both channel area (0.0054mm2) and power (730nW). Delta modulation yields tolerance to input DC offsets of any value, up to the power rail voltage. The differential-difference comparator architecture offers super-GOhm input impedance ensuring that both of the differential inputs transfer functions are well matched, resulting in a superior 78dB rejection of common-mode (CM) signals and artifacts. The highly-oversampling nature of the ADC also renders it insensitive to stimulation artifacts with differential amplitudes of up to 10mV pp , maintaining an ENOB of 9.7 bits and 2.6µV rms integrated input-referred noise. Experimental results validate the key features of the design and include in-vivo recordings in behaving guinea pigs.

A 0.6V 3.8μW ECG/bio-impedance monitoring IC for disposable health patch in 40nm CMOS

Abstract: Simultaneous measurement of Electrocardiogram (ECG) and bio-impedance (BioZ) via disposable health patches is desired for patients suffering from chronic cardiovascular and respiratory diseases. However, a sensing IC must consume ultra-low power under a sub-volt supply to comply with miniaturized and disposable batteries. This work presents a 0.6 V analog frontend (AFE) IC consisting of an instrumentation amplifier (IA), a current source (CS) and a SAR ADC. The AFE can measure ECG and BioZ simultaneously with a single IA by employing an orthogonal chopping scheme. To ensure the IA can tolerate up to 300mVpp DC electrode offset and 400mV pp common-mode (CM) interference, a DC-servo loop (DSL) combined with a common-mode feedforward (CMFF) loop is employed. A buffer-assisted scheme boosts the IA's input impedance by 7x to 140MΩ at 10Hz. To improve the BioZ sensitivity, the CG utilizes dynamic element matching to reduce the 1/f noise of the output current, leading to 35mΩ/√Hz BioZ sensitivity down to 1Hz. The ADC shows a 9.7b ENOB when sampled at 20ksps. The total power consumption of the AFE is 3.8μW.

A 4.06 mW 10-bit 150 MS/s SAR ADC With 1.5-bit/cycle Operation for Medical Imaging Applications

Abstract: This paper reports a 10-bit 150 MS/s successive approximation register analog-to-digital converter with binary-scaled redundancy-facilitated error correction technique. The proposed 1.5-bit/cycle technique with built-in capacitive digital-to-analog converter (CDAC) redundancy, corrects multiple erroneous decisions in a total of nine conversion cycles. The proposed binary-scaled redundancy provides a 12.5% error tolerance range for the incomplete CDAC voltage settling. The digital error-correction logic circuit presented uses a bit-overlap-and-add technique. The prototype chip was fabricated in 65-nm CMOS technology and occupies chip area of 0.038 mm2. It consumes 4.06 mW from a 1.2 V supply, achieving the Nyquist signal-to-noise-and-distortion ratio of 57.81 dB and the effective number of bits of 9.31-bit at an operating frequency of 150 MS/s, corresponding to the figure-of-merit of 42.6 fJ/ conversion-step.

A 15.2-ENOB continuous-time ΔΣ ADC for a 200mV pp -linear-input-range neural recording front-end

Abstract: Closed-loop neuromodulation with simultaneous stimulation and sensing is desired to advance deep brain stimulation (DBS) therapies. However, stimulation generates large artifacts (∼100mV) at the recording sites that saturate traditional front-ends. We present a 15.2b-ENOB CT ΔΣΜ with 187dB FOM, which along with an 8x-gain capacitively coupled chopper instrumentation amplifier (CCIA), realizes a front-end that can digitize neural signals ( pp ) from 1Hz to 5kHz in the presence of 200mV pp artifacts. Neural recording front-ends need to function within a power budget of 10μW/ch, input-referred noise of 4–8μV rms in 1Hz-5kHz, DC input impedance Z in, DC >1GΩ and high-pass (HP) cutoff <1Hz [1]. Prior work has addressed power and noise [1]-[2], but has limited dynamic-range and bandwidth (BW), making them incapable of performing true closed-loop operation.

Mixed-Signal IC With Pulse Width Modulation Wireless Telemetry for Implantable Cardiac Pacemakers in 0.18-μm CMOS

Abstract: A low-power mixed-signal IC for implantable pacemakers is presented. The proposed system features three independent intracardiac signal readout channels with pulse-width-modulated outputs. Also, the proposed system is capable of measuring the amplitude and phase of the bioimpedance with pulse-width-modulated outputs for use in rate adaptive pacemakers. Moreover, a stimulation system is embedded, offering 16 different amplitudes from 1 to 7.8 V. A backscattering transmitter transfers the output signals outside the body with very little power consumption. The proposed low-power mixed-signal IC is fabricated in a 0.18-μm HV CMOS process and occupies 2.38 mm2. The biopotential channels extract the heart signals with 9.2 effective number of bits and the bioimpedance channels measure the amplitude and phase of the heart impedance with 1.35 Ωrms accuracy. The complete IC consumes only 4.2 μA from a 1-V power supply.

Minimally-invasive neural interface for distributed wireless electrocorticogram recording systems

Abstract: This paper presents a minimally-invasive neural interface for distributed wireless electrocorticogram (ECoG) recording systems. The proposed interface equips all necessary components for ECoG recording, such as the high performance front-end integrated circuits, a fabricated flexible microelectrode array, and wireless communication inside a miniaturized custom-made platform. The multiple units of the interface systems can be deployed to cover a broad range of the target brain region and transmit signals via a built-in intra-skin communication (ISCOM) module. The core integrated circuit (IC) consists of 16-channel, low-power push-pull double-gated preamplifiers, in-channel successive approximation register analog-to-digital converters (SAR ADC) with a single-clocked bootstrapping switch and a time-delayed control unit, an ISCOM module for wireless data transfer through the skin instead of a power-hungry RF wireless transmitter, and a monolithic voltage/current reference generator to support the aforementioned analog and mixed-signal circuit blocks. The IC was fabricated using 250 nm CMOS processes in an area of 3.2 × 0.9 mm2 and achieved the low-power operation of 2.5 µW per channel. Input-referred noise was measured as 5.62 µVrms for 10 Hz to 10 kHz and ENOB of 7.21 at 31.25 kS/s. The implemented system successfully recorded multi-channel neural activities in vivo from a primate and demonstrated modular expandability using the ISCOM with power consumption of 160 µW.

Influence of the sampling clock pulse shape mismatch on channel-interleaved photonic analog-to-digital conversion.

Abstract: We investigate the pulse shape mismatch of the sampling clock in channel-interleaved photonic analog-to-digital converters (PADCs) and its influence on the frequency response of the PADC system. Two schemes to generate sampling clock pulses are experimentally implemented to study the influence of the pulse shape mismatch. The scheme with the well-managed pulse shape in all channels is successful in eliminating the influence. Subsequently, a flat 35 GHz frequency response of a four-channel 40 GSa/s PADC is demonstrated, and the effective number of bits reaches 7.7 bits at 11 GHz and 7 bits at 31 GHz.