Showing papers on "Effective number of bits published in 2020"

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier

Abstract: This article presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, voltage, and temperature (PVT)-robust closed-loop dynamic amplifier. The proposed closed-loop dynamic amplifier combines the merits of closed-loop architecture and dynamic operation, realizing robustness, high accuracy, and high energy-efficiency simultaneously. It is embedded in the loop filter of an NS SAR design, enabling the first fully dynamic NS-SAR ADC that realizes sharp noise transfer function (NTF) while not requiring any gain calibration. Fabricated in 40-nm CMOS technology, the prototype ADC achieves an SNDR of 83.8 dB over a bandwidth of 625 kHz while consuming only $107~\mu \text{W}$ . It results in an SNDR-based Schreier figure-of-merit (FoM) of 181.5 dB.

A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog–Digital Corrections in 28-nm CMOS

Abstract: This article presents a 5-GS/s 12-b passive-sampling $8\times $ -interleaved hybrid analog-to-digital converter (ADC) that achieves a low-frequency SFDR/SNDR of 75.2/62.4 dB and a Nyquist SFDR/SNDR of 65.4/58.5 dB. A significant power reduction while attaining a bandwidth in excess of 6 GHz and a high spectral purity are enabled by: 1) an on-chip terminated very fast settling buffer-less input front end; 2) an on-chip clock chain with as low as 11-fs added jitter; 3) an asynchronous three-stage pipelined-successive approximation register (SAR) sub-ADC; and 4) on-chip co-designed analog–digital calibrations deal with sub-ADC and time-interleaving (TI) artifacts to achieve the desired spectral performance levels. The 28-nm bulk CMOS prototype chip occupies a total area of 4.56 mm2 with a core area of 1.76 mm2 and consumes 158.6 mW from a 1-V supply, leading to the Nyquist figure of merits of Schreier (FoMS) and Walden (FoMW) of 160.5 dB and 46.1 fJ/conversion step, respectively.

Fully Synthesizable Low-Area Analogue-to-Digital Converters with Minimal Design Effort Based on the Dyadic Digital Pulse Modulation

Abstract: In this paper, fully-synthesizable Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) suitable for low-cost integrated systems are proposed both for voltage and current input. The proposed ADCs are digital in nature and are based on the Dyadic Digital Pulse Modulation (DDPM) Digital-to-Analog (DAC), instead of a traditional capacitive DAC. The proposed fully-digital ADC architectures enable low-effort design, silicon area reduction, and voltage scaling down to the near-threshold region. Compared to traditional analog-intensive designs, their digital nature allows easy technology and design porting, digital-like area shrinking across CMOS technology generations, and also drastically reduced system integration effort through immersed-in-logic ADC design. The voltage-input ADC architecture is demonstrated with a 40-nm testchip showing 3,000-μm 2 area, 6.4-bit ENOB, 2.8kS/s sampling rate, 40.4dB SNDR, 49.7dB SFDR, and 3.1μW power at 1V. A current-input ADC is also demonstrated for direct current readout without requiring a trans-resistance stage. 40-nm testchip measurements show a 5-nA to 1-μA input range, 4,970μm 2 area, 6.7-bit ENOB and 2.2-kS/s sample rate, at 0.94-μW power. Compared to the state of the art, the proposed ADC architecture exhibits the highest level of design automation (standard cell), lowest area, and the unique ability to cover direct acquisition of both voltage and current inputs, suppressing the need for transresistance amplifier in current readout.

A Robust 8-Bit Non-Volatile Computing-in-Memory Core for Low-Power Parallel MAC Operations

Abstract: The Artificial Intelligence (AI) in edge computing is requesting new processing units with a much higher computing-power ratio. The emerging resistive Non-Volatile Memory (NVM) with the in-memory computing capability may greatly advance the AI hardware technologies. In this paper, we propose the use of binary resistive memory to form an 8-bit fixed-point data/weight for AI computing. A robust Computing-In-Memory (CIM) core with digital input and analog output Multiplication-and-Accumulation (MAC) circuit is proposed. The corresponding integration scheme and Successive Approximation Register Analog-to-Digital Converter (SAR ADC) based data conversion scheme are also presented. The simulation results show that the proposed CIM core achieves 7.26 bit of Effective Number of Bits (ENOB) with 0.78mW (256*1) power consumption and 1.85M/s computing speed. Compared with previously reported CIM implementations and Deep Learning Accelerators (DLAs) (without CIM ability), our design achieves 2.23– $7.26\times $ better energy efficiency in 8-bit input 8-bit weight pattern, and achieves relatively high accuracy with LeNet and AlexNet.

9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier

Abstract: Noise shaping (NS) SAR ADCs combine the merits of SAR and Δσ ADCs, and can simultaneously achieve high power efficiency and high resolution. The key operation in an NS SAR is the residue integration. One way to implement it is to use a conventional closed-loop OTA [1]–[2]. It is robust against PVT variation and can realize a sharp noise transfer function (NTF), but it consumes static power and is does not scale easily. Another way is to use a passive filter [3]–[4]. It does not consume any static current, but its NTF is less aggressive. Moreover, because the gain of a passive filter is low, its suppression of the comparator noise is weak. An open-loop dynamic amplifier (DA) can be placed before the passive filter to reduce noise and power, but its gain varies with PVT [5]–[6]. To ensure stability, the NTF needs to be mild, which limits the NS performance [5], or background calibration has to be used, which increases the design complexity and requires a large number of samples to converge [6]. In addition, without complete settling, the gain of an open-loop DA is sensitive to timing error, e.g. clock jitter.

A 0.36-V 5-MS/s Time-Mode Flash ADC With Dickson-Charge-Pump-Based Comparators in 28-nm CMOS

Abstract: Dickson charge-pump (CP) is proposed here to realize a voltage-to-time converter (VTC) within an array of time-domain comparators of a 54-level time-mode subthreshold flash ADC operating at 0.36V. Two identical CPs in each of the 54 ADC slices convert the input and reference voltages into variable-slope ramp signals fed into comparators for ‘flash’ quantization. Considering the fact that the comparator’s evaluation time gets severely degraded at subthreshold input voltages, the proposed ADC delivers the maximum bandwidth by means of the inherent input voltage boosting by the Dickson CPs. The proposed architecture quantizes the analog input signal into time with CPs and then into digital domain with latches and simple logic, without using any analog-intensive circuits such as amplifiers and current sources, thus yielding a digitally friendly implementation. Measurement results show peak ENOB of 5.04-bit, SNDR of 32.1dB at the peak, power consumption of $88~\mu \text{W}$ . The conversion rate of 5 MS/s is the highest among near- and subthreshold ADCs.

Demonstration of a wideband submillimeter-wave low-noise receiver with 4-21 GHz IF output digitized by a high-speed 32 GSps ADC

Abstract: We report on a 275–500 GHz heterodyne receiver system in combination with a wideband intermediate-frequency (IF) backend to realize 17 GHz instantaneous bandwidth. The receiver frontend implements a heterodyne mixer module that integrates a superconductor-insulator-superconductor (SIS) mixer chip and a cryogenic low-noise preamplifier. The SIS mixer is developed based on high-current-density junction technologies to achieve a wideband radio frequency (RF) and IF bandwidth. The IF backend comprises an IF chain divided into two channels for 4.0–11.5 GHz and 11.3–21.0 GHz and an analog-to-digital converter (ADC) module that is capable of high-speed sampling at 32 Giga samples per second with 12.5 GHz bandwidth per channel and an effective number of bits of 6.5. The IF backend allows us to simultaneously cover the full 4–21 GHz IF range of the receiver frontend. The measured noise temperature of the receiver frontend was below three times the quantum noise (hf /k B ) over the entire RF band. A dual-polarization sideband-separating receiver based on this technique could provide up to 64 GHz of instantaneous bandwidth, which demonstrates the possibility of future wideband radio astronomical observations with advanced submillimeter-wave heterodyne receivers.

A 0.3V 10b 3MS/s SAR ADC With Comparator Calibration and Kickback Noise Reduction for Biomedical Applications

Abstract: This paper presents a 10-bit successive approximation analog-to-digital converter (ADC) that operates at an ultralow voltage of 0.3 V and can be applied to biomedical implants. The study proposes several techniques to improve the ADC performance. A pipeline comparator was utilized to maintain the advantages of dynamic comparators and reduce the kickback noise. Weight biasing calibration was used to correct the offset voltage without degrading the operating speed of the comparator. The incorporation of a unity-gain buffer improved the bootstrap switch leakage problem during the hold period and reduced the effect of parasitic capacitances on the digital-to-analog converter. The chip was fabricated using 90-nm CMOS technology. The data measured at a supply voltage of 0.3 V and sampling rate of 3 MSps for differential nonlinearity and integral nonlinearity were +0.83/−0.54 and +0.84/−0.89, respectively, and the signal-to-noise plus distortion ratio and effective number of bits were 56.42 dB and 9.08 b, respectively. The measured total power consumption was 6.6 μW at a figure of merit of 4.065 fJ/conv.-step.

A 5-GS/s 7.2-ENOB Time-Interleaved VCO-Based ADC Achieving 30.5 fJ/cs

Abstract: This article presents an eight-channel time-interleaved voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC), achieving 7.2 effective number of bits (ENOBs) at 5 GS/s in 28-nm CMOS. A high-speed ring oscillator with feedforward cross-coupling and a shared tail transistor is combined with an asynchronous counter in order to improve the resolution while minimizing the power consumption. Asynchronous double sampling is used to enable reliable sampling of the asynchronous counter state. On-chip digital calibration is used to compensate for channel mismatch and nonlinear distortion, and sampling time mismatch is corrected using tunable clock delays. With a total power consumption of just 22.7 mW, it achieves a Walden figure-of-merit (FOM) of 30.5 fJ/cs.

A 16.1-bit Resolution 0.064-mm 2 Compact Highly Digital Closed-Loop Single-VCO-Based 1-1 Sturdy-MASH Resistance-to-Digital Converter With High Robustness in 180-nm CMOS

Abstract: A novel direct resistive-sensor-to-digital readout circuit is presented, which achieves 16.1-bit ENOB while being very compact and robust. The highly digital time-based architecture employs a single voltage-controlled oscillator (VCO), counter, and digital feedback loop for the readout of an external single-ended highly nonlinear resistive sensor, such as an NTC thermistor. In addition to the inherent first-order noise shaping due to the oscillator, the second loop in SMASH configuration creates second-order noise shaping. Fabricated in 180-nm CMOS, the readout circuit achieves 16.1 bit of resolution for 1-ms conversion time and consumes only $171~\mu \text{W}$ , resulting in an excellent 2.4-pJ/c.s. FOMW for a resistive sensor interface while occupying only 0.064 mm 2. The specific closed-loop architecture tackles the VCO nonlinearity, achieving more than 14 bits of linearity. Multiple prototype chip samples have been measured in a temperature-controlled environment from −40 °C to 125 °C for the readout of commercial external NTC thermistors. A maximum temperature inaccuracy of 0.3 °C is achieved with only one-point trimming at room temperature. Since the circuit architecture decouples the sensor excitation from the feedback, high electromagnetic interference (EMI) immunity at the sensor node is demonstrated as well.

Analysis and Design of an All-Digital ∆Σ TDC via Time-Mode Signal Processing

Abstract: This brief presents an all-digital first-order 1-bit $\Delta \Sigma $ time-to-digital converter (TDC) using a time-mode signal processing approach. Time integration is performed using a bi-directional gated delay line. The nonlinearity and timing errors of the time integrator are analyzed. The impact of feedback time on the performance of the TDC is analyzed. A design methodology effective in minimizing the impact of process uncertainty is developed. The TDC is designed in a TSMC 130-nm 1.2-V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results show the TDC offers SNDR of 50.0 dB and ENOB of 8.0 over 731-kHz bandwidth at 33-MHz sampling frequency while consuming 175 $\mu \text{W}$ . The FOM of the TDC is 0.47 pJ/conv.

A −68 dB THD, 0.6 mm 2 Active Area Biosignal Acquisition System With a 40–320 Hz Duty-Cycle Controlled Filter

Abstract: This paper presents a reconfigurable front-end (FE) circuit for acquiring various low-frequency biomedical signals. An energy and area-efficient tunable filter is proposed for adapting the FE bandwidth to the signal of interest. The filter is designed using a switched-R-MOSFET-C (SRMC) technique to realize the needed ultra-low cutoff frequency. An 8-bit SAR ADC, following the filter, quantizes the signal, while the SAR control logic is re-used to accurately program the filter bandwidth from 40 Hz to 320 Hz with a 40 Hz step. The prototype chip includes the complete FE system, formed of an instrumentation amplifier (IA), a programmable-gain amplifier (PGA), and the proposed tunable filter followed by the SAR ADC. Implemented in 0.13 $\mu \text{m}$ CMOS technology, the IC occupies a 0.6 mm2 active area while consuming 6.3 $\mu \text{W}$ dc power from a 2-V supply. Measurement results show a FE gain range of 43–55 dB with an integrated input-referred noise ( ${V_{\text {IRN}}}$ ) of 3.45 $\mu V_{\text {rms}}$ , a 66 dB dynamic range (DR), and a total-harmonic distortion (THD) of −68 dB at an input amplitude of 6 $\text{m}V_{PP}$ . The effective number of bits (ENOB) for the ADC is 7.921 bits at 1-kS/s. In real-time Electrocardiogram (ECG), Electromyography (EMG), and Electroencephalography (EEG) measurements, high-fidelity waveforms are acquired using the proposed FE IC, validating the system’s reconfigurability and high-linearity.

A Design of 8 fJ/Conversion-Step 10-bit 8MS/s Low Power Asynchronous SAR ADC for IEEE 802.15.1 IoT Sensor Based Applications

Abstract: An energy efficient, low-power 10-bit asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter with the sampling frequency of 8 MS/s is presented for IEEE 802.15.1 IoT sensor based applications. An improved common mode charge redistribution algorithm is proposed for binary weighted SAR ADC. The proposed method uses available common mode voltage (VCM) level for SAR ADC conversion, and this method reduces the switching power by more than 12% without any additional DAC driver as compared to merged capacitor switching (MCS). Mathematical analysis of the proposed switching scheme results in the lower or equal power consumption for every digital code as compared to MCS. A two stage dynamic latched comparator with adaptive power control (APC) technique is used to optimize the overall efficiency. Furthermore, to minimize the digital part power consumption, a modified asynchronous SAR logic with digitally controlled delay cells is proposed. High efficiency with low power consumption makes it suitable for low power devices especially for IEEE 802.15.1 IoT sensor based applications. The proposed prototype is implemented using 1P6M 55 nm complementary metal-oxide-semiconductor (CMOS) technology. The measurement results that the proposed circuit achieves are 9.3 effective number of bits (ENOB) with signal-to-noise and distortion ratio (SNDR) of 58.05 dB at a sampling rate of 8 MS/s. The power consumption of SAR ADC is $45~\mu \text{W}$ when operated at 1 V power supply.

A 12-bit SAR ADC With a DAC-Configurable Window Switching Scheme

Abstract: This paper presents a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) that uses a digital-to-analog converter (DAC) configurable window switching technique. By reusing the capacitors in the DAC, the proposed window switching scheme yields window boundaries to determine whether the input is located within the window, and thus avoid unnecessary capacitor switching. The proposed window SAR ADC improves the conversion efficiency and ADC linearity. A qualitative analysis of prior window switching schemes is presented to elaborate for various applications. A low-input capacitance of 1 pF was adopted to relax the input and reference buffers. A prototype ADC was implemented in 180-nm CMOS occupying an active area of 0.1 mm2. At 20 MS/s, it consumes a total power of 1.22 mW from a 1.5-V supply. The measured peak signal-to-noise and distortion ratio and spurious-free dynamic range were 61.7 and 79 dB, respectively. At the Nyquist rate, the measured effective number of bits (ENOB) was 9.53, equivalent to a figure-of-merit (FOM) of 83 fJ/conversion-step. In low-power mode (100 kS/s), it consumed a total power of $1.5~\mu \text{W}$ from a 0.7-V supply. At the Nyquist rate, the measured ENOB was 9.82, equivalent to a FOM of 16.6 fJ/conversion step.

A 120 GS/s 2:1 Analog Multiplexer with High Linearity in SiGe-BiCMOS Technology

Abstract: A 2:1 analog multiplexer (AMUX) in SiGe BiCMOS technology with a record sampling rate for SiGe-technology of 120 GS/s, is presented. The AMUX is intended to double the signal bandwidth of two 8-bit digital-to-analog-converters and achieves an effective resolution (ENoB) of 7.7 bit, at low frequencies as well as 5.1 bit at 48.8 GHz and 4.1 bit at 58.6 GHz for sampling rates of 100 GS/s and 120 GS/s, respectively. These are the highest resolutions reported for an AMUX in any kind of semiconductor technology. The results were obtained by a simple selector-circuit concept that was carefully optimized in the frequency domain with regard to balanced signal paths. The AMUX performance was demonstrated by measurements on an RF-module bondwire-assembly of the AMUX-chip.

Relaxation Digital-to-Analog Converter with Foreground Digital Self-Calibration

Abstract: A reference-free, fully digital foreground self-calibration strategy intended to automatically tune the clock frequency of Relaxation Digital to Analog Converters (ReDACs), as demanded for linear operation, is presented in this paper. The effectiveness of the proposed approach is demonstrated by computer simulations on a 10-bit, 2MS/s ReDAC designed in 40nm CMOS and operated from a 600mV power supply voltage. After the proposed calibration, the ReDAC is shown to operate near the optimal clock frequency achieving 0.98 LSB maximum INL, 1.00 LSB maximum DNL and 9.06 ENOB.

A 0.5 V 10-bit 3 MS/s SAR ADC With Adaptive-Reset Switching Scheme and Near-Threshold Voltage-Optimized Design Technique

Abstract: This brief presents a 10-bit ultra-low power energy-efficient successive approximation register (SAR) analog-to-digital converter (ADC). A new adaptive-reset switching scheme is proposed to reduce the switching energy of the capacitive digital-to-analog converter (CDAC). The proposed adaptive-reset switching scheme reduces the average switching energy of the CDAC by 90% compared to the conventional scheme without the common-mode voltage variation. In addition, the near-threshold voltage (NTV)-optimized digital library is adopted to alleviate the performance degradation in the ultra-low supply voltage while simultaneously increasing the energy efficiency. The NTV-optimized design technique is also introduced to the bootstrapped switch design to improve the linearity of the sample-and-hold circuit. The test chip is fabricated in a 65 nm CMOS, and its core area is 0.022 mm2. At a supply of 0.5 V and sampling speed of 3 MS/s, the SAR ADC achieves an ENOB of 8.78 bit and consumes $3.09~{\boldsymbol{\mu }}\text{W}$ . The resultant Walden figure-of-merit (FoM) is 2.34 fJ/conv.-step.

A Closed-Loop Capacitance-to-Frequency Converter for Single-Element and Differential Capacitive Sensors

Abstract: A novel closed-loop switched-capacitor (SC) capacitance-to-frequency converter (CFC) is presented in this article. The proposed CFC is capable of measuring from either a single-element or a differential capacitive sensor (DCS), providing ratio and ratiometric outputs, respectively. Most of the existing autobalancing schemes for capacitive sensors use the closed-loop approach but require precise sinusoidal ac excitation and provide an analog output that is sensitive to parasitic capacitances. Also, the use of voltage-controlled resistors (VCRs) in many of these schemes limits the linearity and accuracy of their output. The SC-CFC presented in this article employs a simple dc reference for excitation and gives a digital output that is insensitive to parasitic capacitances, by virtue of design. Additionally, the output is linear, irrespective of the sensor characteristic, and independent of the nominal value of the sensor. This feature, along with its compatibility with single-element and DCSs, facilitates its ease of integration with a wide range of capacitive sensors. The CFC has a one-time correction mechanism that significantly reduces the impact of component mismatch. The prototype of the proposed scheme exhibits a maximum nonlinearity error (NLE) of 0.24%, a resolution of 12.59 effective number of bits (ENOB), and a rise time of 6 ms. In addition, the proffered design is fit for integrated circuit (IC) fabrication as it employs an SC approach.

A 12-Bit Dynamic Tracking Algorithm-Based SAR ADC With Real-Time QRS Detection

Abstract: A 12-bit successive approximation register (SAR) ADC based on dynamic tracking algorithm and a real-time QRS-detection algorithm are proposed. The dynamic tracking algorithm features two tracking windows which are adjacent to prediction interval. This algorithm is able to track down the input signal’s variation range and automatically adjust the subrange interval and update prediction code. QRS-complex detection algorithm integrates synchronous time sequential ADC and real-time QRS-detector. The chip is fabricated in a standard 0.13 $\mu \text{m}$ CMOS process with a 0.6 V supply. Measurement results show that proposed ADC exhibits 10.72 effective number of bit (ENOB) and 79.63 dB spur-free dynamic range (SFDR) at 10k Hz sample rate given 41.5 Hz sinusoid input. The DNL and INL are bounded at −0.6/0.62 LSB and −0.67/1.43 LSBs. The ADC achieves FoM of 48 fJ/conversion-step at the best case. Also, the prototype is experimented with ECG signal input and extracts the heart beat signal successfully.

Analog Vector-Matrix Multiplier Based on Programmable Current Mirrors for Neural Network Integrated Circuits

Abstract: We propose a CMOS Analog Vector-Matrix Multiplier for Deep Neural Networks, implemented in a standard single-poly 180 nm CMOS technology. The learning weights are stored in analog floating-gate memory cells embedded in current mirrors implementing the multiplication operations. We experimentally verify the analog storage capability of designed single-poly floating-gate cells, the accuracy of the multiplying function of proposed tunable current mirrors, and the effective number of bits of the analog operation. We perform system-level simulations to show that an analog deep neural network based on the proposed vector-matrix multiplier can achieve an inference accuracy comparable to digital solutions with an energy efficiency of 26.4 TOPs/J, a layer latency close to $100~\mu \text{s}$ and an intrinsically high degree of parallelism. Our proposed design has also a cost advantage, considering that it can be implemented in a standard single-poly CMOS process flow.

A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application

Abstract: A design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching technique is proposed. The proposed switching technique consumes only 63.75 CVREF2 switching energy, which is far less as compared to the conventional switching technique without dividing or adding additional switches. In addition, bootstrap switching is implemented to ensure enhanced linearity. To reduce the power consumption from the comparator, a dynamic latch comparator with a self-comparator clock generation circuit is implemented. The proposed prototype of the SAR ADC is implemented in a 55 nm CMOS (complementary metal-oxide-semiconductor) process. The proposed architecture achieves a figure of merit (FOM) of 17.4 fJ/conversion, signal-to-noise distortion ratio (SNDR) of 60.39 dB, and an effective number of bits (ENOB) of 9.74 bits with a sampling rate of 1 MS/s at measurement levels. The implemented SAR ADC consumes 14.8 µW power at 1 V power supply.

A Power-Efficient Bridge Readout Circuit for Implantable, Wearable, and IoT Applications

Abstract: A power-efficient bridge-to-digital sensing interface is proposed, which also offers immunity against power supply noise. The interface utilizes duty-cycling to reduce the static power consumption of resistive bridge sensors, which are commonly used in implantable, wearable, and internet of things (IoT) applications, such as intracranial pressure (ICP) sensing and blood pressure (BP) monitoring. The proposed interface uses a revised version of the pseudo-pseudo differential (PPD) topology with the ping-pong technique to reduce the complexity of traditional fully-differential counterparts. A proof-of-concept prototype has been fabricated in 0.35- $\mu \text{m}$ CMOS and occupies an active area of 0.48 mm2. It achieves 9.13 effective number of bits (ENOB) at 3.72 kHz sampling rate and improvement of more than 50 dB in the power supply rejection ratio (PSRR) by employing the ping-pong technique. It reduces the power consumption of a 5- $\text{k}\Omega $ Wheatstone bridge by 99.6% compared to a traditional interface, down to $2.53~\mu \text{w}$ at 1.8 V supply. The functionality of the system has also been demonstrated in an experimental setup in conjunction with an embedded resistive bridge pressure sensor.

A Low Voltage and Low Power 10-bit Non-Binary 2b/Cycle Time and Voltage Based SAR ADC

Abstract: This paper proposes a low power 10-bit 2b/cycle time and voltage based-successive approximation register (SAR) analog-to-digital converter (ADC). At low supply voltage, there will be a significant difference in comparator decision time for different input voltages. By taking advantage of the fact, this ADC converts the reference voltage to the corresponding comparator decision time, achieving 2b/cycle quantization to improve the conversion speed. In addition, by obtaining reference delays with duplicated circuits and using non-binary capacitor arrays, the ADC can tolerate process, voltage and temperature (PVT) variations and decision errors. To validate these concepts, a 10-bit 2MS/s SAR ADC is designed using 130nm CMOS process with 0.5V power supply voltage. Measured results show that the ADC can work normally from 0.5V to 1V supply voltage, with the sampling rate increasing from 2MS/s to 32MS/s. The ADC achieves an SNDR (signal-to-noise distortion ratio) of 56.7dB, corresponding to an ENOB (effective number of bits) of 9.13 bits and consumes $3.4\mu \text{W}$ , resulting in a figure of merit (FoM) of 3.03 fJ/c.-s at 0.5V supply voltage and 2MS/s sampling rate.

Photonic digital-to-analog conversion using a blue frequency chirp in a semiconductor optical amplifier.

Abstract: In this Letter, we present a photonic digital-to-analog conversion (DAC) technique based on blue-chirp spectral slicing using a semiconductor optical amplifier (SOA). Because the gain change in an SOA leads to a refractive-index change based on the change in intensity of the input data signal, the probe signals experience a dynamic frequency shift to a shorter-wavelength side called a blue-chirp. After passing through the SOA, the probe signals corresponding to the logic level of the input digital signal are extracted by filtering only the blue-chirp component of the probe signals using rectangular-shape filters. In this study, we experimentally demonstrate a 10-Gb/s, 2-bit photonic DAC from a 10-Gb/s digital signal with various data patterns to a four-level amplitude signal assuming an analog signal. In addition, we evaluate the resolution performance of the photonic DAC in terms of differential and integral nonlinearities and an effective number of bits.

Design of a Low Power 10-b 8-MS/s Asynchronous SAR ADC with On-Chip Reference Voltage Generator

Abstract: This paper presents an energy-efficient low power 10-b 8-MS/s asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter. An inverted common-mode charge recovery technique is proposed to reduce the switching energy and to improve the linearity of the digital-to-analog converter (DAC). The proposed switching technique consumes only 149 CVREF2 switching energy for the 10-bit case. A rail-to-rail dynamic latch comparator is implemented with adaptive power control for better power efficiency. Additionally, to optimize the power consumption and performance of the logic part, a modified asynchronous type SAR control logic with digitally controllable delay cells is adopted. An on-chip reference voltage generator is also designed with an ADC core for practical use. The structure is realized using 55-nm complementary metal–oxide–semiconductor (CMOS) process technology. The proposed architecture achieves an effective number of bits (ENOB) of 9.56 bits and a signal-to-noise and distortion ratio (SNDR) level of 59.3 dB with a sampling rate of 8 MS/s at measurement level. The whole architecture consumes only 572 µW power when a power supply of 1 V is applied.

A Low-Power Time-to-Digital Converter for Sensor Interface Circuits

Abstract: This brief proposes a new low-power time-to-digital converter (TDC). In contrast to the previous works that digitize each new input sample independent of the previous ones, the proposed structure obtains the digital code of the new sample based on the difference between the previous sample and the new one. Therefore, since the activity of the circuit is reduced, its power consumption is saved, especially for the applications that the variation of the input signal is usually much smaller than the signal range, such as sensor interface circuits. Based on the proposed structure, a 200 kS/s TDC circuit with a resolution of 3.2 ps is designed and simulated in a 65-nm CMOS technology. Post-layout simulation results show that the proposed structure achieves an effective number of bits (ENOB) of 7.52 bits at the cost of 10.1 $\mu \text{W}$ power consumption. Moreover, the effective area occupied by the circuit is 110 $\mu \text{m}\,\,\times $ 130 $\mu \text{m}$ .

Frequency Dependent ENoB Requirements for 400G/600G/800G Optical Links

Abstract: Electronic converters (ECs), such as Digital-to-Analog Converters (DACs) and Analog-to-Digital Converters (ADCs), have become essential components in high-speed optical communication systems. However, with increasing operating symbol rates and modulation formats, frequency dependent ENoB such as those demonstrated by wideband ECs begin to impair signal quality significantly. Understanding these impairments is crucial for future optical link planning and deployment. Here, we present a novel ADC model that can simulate frequency dependent ENoB in optical links. The model is both theoretically and experimentally validated. Using such models, we demonstrate the effects of wideband ECs on 64 GBaud DP-16QAM (400G), 64 GBaud DP-64QAM (600G), and 96 GBaud DP-32QAM (800G). Furthermore, we present a machine learning based regression that can analytically obtain EC induced penalties for these investigated systems.

An 8.2- $\mu$ W 0.14-mm 2 16-Channel CDMA-Like Capacitance-to-Digital Converter

Abstract: This article presents a multi-channel capacitance-to-digital converter (CDC) circuits using the continuous-time Walsh coding multiplexing. The proposed circuits modulate the input capacitive sensors with orthogonal codes, enable simultaneous read-in of 16 capacitive sensors, and provide the combined 16 digitized outputs in a single conversion. By correlating 16 successive digitized outputs with the corresponding orthogonal codes in post-processing, the 16 capacitive channels can then be demodulated separately. The proposed continuous-time Walsh coding modulation preserves temporal information with minimum circuitry duplication and bandwidth requirement. This chip is fabricated in 130-nm CMOS technology and occupies an area of 0.14 mm2. With a reference clock of 4 MHz, the proposed multi-channel CDC achieves 11.4 ENOB with an average conversion time of 482 $\mu \text{s}$ . It consumes 0.51 $\mu \text{W}$ /channel and achieves an FoM of 87 fJ/conversion step.

Evaluation of a Digitizer Designed to Interface a Non-Intrusive AC Voltage Measurement Probe

Abstract: A low-cost yet efficient digitizer, suitable for a capacitive type non-contact ac voltage probe is presented. The existing measurement scheme for such a probe requires an interfacing circuit, an analog-to-digital converter followed by a processor to compute fast Fourier transform (FFT) to obtain an output. It will be beneficial and less complex if an analog to digital converter can be developed that can directly interface with the probe and get the final output without FFT computation. Such a scheme that operates based on the dual-slope analog-to-digital conversion technique is presented in this paper. Its output is directly proportional to the fundamental component of the unknown ac voltage. Output has negligible sensitivity to the variations in the probe-to-wire capacitance. The proposed scheme has a new and simple compensation approach to accurately obtain the fundamental of the unknown voltage, even if it has significant 3rd harmonics. A detailed analysis of various sources of errors affecting the performance of the scheme is conducted and the details are presented in the paper. A prototype of the proposed scheme has been designed, developed and interfaced with a laboratory-made non-intrusive ac voltage probe and tested for 0–600 V, at two frequencies, 50 Hz and 60 Hz. The output of the digitizer was linear, with worst-case linearity of 0.26%. The effective number of bits observed for the prototype were 11.16 and 11.85 for 50 Hz and 60Hz measurement respectively.