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Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.


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Patent
Kalevo Ossi1
09 Jan 2004
TL;DR: In this paper, the number of bits is limited in the bit string of a pixel to be processed, wherein the pixel is encoded with the limited number of bit. In the method, a prediction value corresponding to said pixel is searched for. If it is found, the difference between the pixel and the prediction value is determined, to select the method for encoding the bit strings of said pixel.
Abstract: The invention relates to a method as well as a system, a device, an encoder and a decoder, and a computer software product for image processing by the method. In the invention, the number of bits is limited in the bit string of a pixel to be processed, wherein the pixel is encoded with the limited number of bits. In the method, a prediction value corresponding to said pixel is searched for. If it is found, the difference between the pixel and the prediction value is determined, to select the method for encoding the bit string of said pixel. Also, a code word is encoded in the bit string, to indicate the selected encoding method. If the predicThe invention relates to a method as well as a system, a device, an encoder and a decoder, and a computer software product for image processing by the method. In the invention, the number of bits is limited in the bit string of a pixel to be processed, wherein the pixel is encoded with the limited number of bits. In the method, a prediction value corresponding to said pixel is searched for. If it is found, the difference between the pixel and the prediction value is determined, to select the method for encoding the bit string of said pixel. Also, a code word is encoded in the bit string, to indicate the selected encoding method. If the prediction value is missing, the number of bits in said pixel is limited by quantizing. By means of the invention, a fixed number of bits is obtained for all encoded pixels in an image.

23 citations

Patent
01 May 2000
TL;DR: In this article, a method of transmitting data over a communications channel, at least some of the bits of an incoming bit stream are passed through a turbo encoder to generate turbo encoded output bits.
Abstract: In a method of transmitting data over a communications channel, at least some of the bits of an incoming bit stream are passed through a turbo encoder to generate turbo encoded output bits, and words corresponding to symbol points on a constellation in a trellis code modulation scheme are generated using at least the bits passed through the turbo encoder, possibly in conjunction with other bits that are not passed the through the turbo encoder. Typically, the turbo encoded bits are the least significant bits.

23 citations

Proceedings ArticleDOI
09 Oct 2009
TL;DR: The proposed multipath frequency-compensation technique enables the conventional RNMC-based three-stage amplifier to achieve a stable operation at a sampling rate of 160MS/s, and the measured differential and integral nonlinearities of the prototype ADC implemented in a 65nm CMOS process are less than 0.2V.
Abstract: A 12-bit 1.2V 160MS/s pipeline ADC for high-definition video systems is presented. The proposed multipath frequency-compensation technique enables the conventional RNMC-based three-stage amplifier to achieve a stable operation at a sampling rate of 160MS/s. The measured differential and integral nonlinearities of the prototype ADC implemented in a 65nm CMOS process are less than 0.69LSB and 1.00LSB respectively. The ADC shows a maximum SNDR of 58.5dB and 53.1dB and a maximum SFDR of 76.0dB and 67.8dB at 160MS/s and 200MS/s, respectively. The ADC with an active die area of 0.72mm2 shows a FoM of 0.75pJ/conv-step at 160MS/s and 1.2V.

23 citations

Patent
J En1
11 Jun 1973
TL;DR: In this paper, an error detecting coding and decoding system employing an encoder having a plurality of shift register systems for generating independent sequences of check bits for multiple level checks is presented, and a decoder having similar shift registers is employed to regenerate the check bits from the transmitted information and compare the locally generated check bits with the transmitted check bits generated by the encoder.
Abstract: An error detecting coding and decoding system employing an encoder having a plurality of shift register systems for generating independent sequences of check bits for multiple level checks. A decoder having similar shift registers is employed to regenerate the check bits from the transmitted information and to compare the locally generated check bits with the transmitted check bits generated by the encoder.

23 citations

Patent
24 Feb 1989
TL;DR: In this paper, a comparator/multiplexer section compares the comparison signals against ground, selects one of the comparison signal and produces a code, and an amplifier amplifies the selected comparison signal.
Abstract: This multi-flash analog-to-digital converter (ADC), in particular dual flash ADC, has extremely high speed and resolution. The final resolution of a comparator/multiplexer section can be effectively doubled. For instance, a 16-bit ADC can employ 300 rather than 255 comparators. A monolithic integration can be accomplished. A resistive network is coupled to a current source and to a reference signal for providing a plurality of comparison signals. A comparator/multiplexer section compares the comparison signals against ground, selects one of the comparison signals and produces a code. An amplifier amplifies the selected comparison signal. A switch provides the reference signal in response to the ADC input signal and subsequently in response to the amplifier output signal. Two codes are encoded and converted into the output code of the ADC.

23 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202361
2022143
202196
2020147
2019149
2018147