scispace - formally typeset
Search or ask a question
Topic

Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.


Papers
More filters
Patent
13 Aug 2001
TL;DR: In this paper, a reduced state equalizer is used for soft bit computation with decision-feedback equalization, and the soft decision-making is used to compute the second set of soft bits.
Abstract: Method and apparatus for soft bit computation with a reduced state equalizer. The method assures that the number of states in the equalizer is reduced to obtain acceptable complexity, while also ensuring that soft bit computation is performed for substantially all bits. The method involves computing a first set of soft bits from bits transmitted in a received signal, using a reduced-state trellis with finite non-zero delay, calculating hard decisions in response to the received signal, and also ensuring that substantially all soft bits are computed by employing zero-delay soft decision-making or decision-feedback equalization to compute a second set of soft bits. Furthermore, the hard decisions are used to compute the second set.

23 citations

Patent
24 Sep 1993
TL;DR: In this article, an improved sigma-delta analog-to-digital converter (ADC) is described, which includes a dither circuit fabricated within the package of the ADC.
Abstract: An improved sigma-delta analog-to-digital converter (ADC) is disclosed herein. The digital converter includes a dither circuit fabricated within the package of the ADC. The circuit is configured to apply a dither current to the analog input of the ADC. The frequency of the dither current is selected based upon the bandwidth of the analog signals for which the ADC is designed to sample and convert to digital signals. Application of the dither current to the input of the ADC reduces quantization noises produced as a result of certain ranges of DC offset voltages found within analog signals applied to the ADC.

22 citations

Patent
Satoshi Tamaki1, Takashi Yano1
03 Mar 2006
TL;DR: In this paper, the pilot signal is used as a reference phase of demodulation in a multi-carrier communication system such as OFDM, and information that requires a high communication quality such as the systematic bits is mapped to carriers having a frequency close to the carriers.
Abstract: A communication quality is improved or signal processing is simplified in a multi-carrier communication system such as OFDM. Information different in communication quality such as systematic bits and parity bits of turbo encoded code words is combined together, and information that requires a high communication quality such as the systematic bits is mapped to carriers having a frequency close to the carriers in which the pilot signal exists used as a reference phase of demodulation than the information such as the parity bits which does not require the high communication quality such as the systematic bits.

22 citations

Journal ArticleDOI
TL;DR: In this work, an asynchronous digital slope architecture is introduced that only requires a nonoversampled clock, thus enabling a much higher speed of operation and enabling very good power-efficiency without using complex calibration techniques.
Abstract: Slope and digital-ramp converters are normally limited to very low sampling rates, since they require a digital counter at a highly oversampled clock rate. In this work, an asynchronous digital slope architecture is introduced that only requires a nonoversampled clock, thus enabling a much higher speed of operation. At the same time, the low complexity and the inherent accuracy of the slope-architecture enable very good power-efficiency without using complex calibration techniques. A two-channel time-interleaved 5-bit asynchronous digital slope ADC was implemented in a 90-nm CMOS technology and occupies 160 μm × 200 μm. The measured prototype achieves an ENOB of 4.6 bit, while operating at 250 MS/s and consuming 0.8 mW from a 1-V supply.

22 citations

Proceedings ArticleDOI
E. Seifert1, A. Nauda1
01 Jun 1989
TL;DR: A technique for improving the dynamic range of analog-to-digital converters (ADCs) by summing outputs of several parallel N-bit ADCs to reduce the uncorrelated excess noise introduced by each ADC.
Abstract: A technique for improving the dynamic range of analog-to-digital converters (ADCs) is presented. The technique consists of summing outputs of several parallel N-bit ADCs to reduce the uncorrelated excess noise introduced by each ADC. This increases the number of effective bits of resolution and is most useful to regain bits lost after dithering to reduce spurious harmonics for spectral analysis applications. The sensitivity of this approach to uncertainties in component gain and delay is discussed. >

22 citations


Network Information
Related Topics (5)
CMOS
81.3K papers, 1.1M citations
94% related
Integrated circuit
82.7K papers, 1M citations
88% related
Amplifier
163.9K papers, 1.3M citations
88% related
Electronic circuit
114.2K papers, 971.5K citations
87% related
Transistor
138K papers, 1.4M citations
85% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202361
2022143
202196
2020147
2019149
2018147