Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

Pulse density modulation based digital-to-analog conversion

Abstract: An approach for converting an M-bit digital input value into an analog output signal involves separately processing the (M-N) number of most significant bits and the N number of least significant bits of the M-bit digital input value. The N number of least significant bits are converted by a pulse density modulator (102) into a pulse density modulated signal. The pulse density modulated signal is processed by a filter (104) to provide a first analog signal. The (M-N) number of most significant bits are processed by a static digital-to-analog converter (106) to provide a second analog signal. The first and second analog signals are combined (108) to provide the analog output signal.

Reducing the effect of elements mismatch in a sar adc

Abstract: An intermediate set of bits of a SAR ADC are converted into first intermediate analog value and a second intermediate analog value respectively from a first set of representative capacitor and a second set of representative capacitor A capacitor in the first set and second set are selected as not same A SAR ADC output code is generated from the first intermediate analog value and the second intermediate analog value The resolution of a N bit SAR ADC can be enhanced by generating more than one N bits digital codes correspondingly operating the N Bit SARADC with more than on transfer functions Each transfer function is selected such that they are offset by a fraction of LSB value The more than one N bits digital codes are then added to form P bits digital code such that P is greater than N due to addition

Semiconductor memory device having function of checking and correcting error of read-out data

Abstract: A semiconductor memory device includes a memory cell array; a sense amplifying circuit, operatively connected to the memory cell array, for sensing the information bits and the check bits; a latch circuit, operatively connected to the sense amplifying circuit, for latching the information bits and the check bits sensed by the sense amplifying circuit; and a circuit for correcting an error in logical level in the information bits. The latch circuit latches the logical level of the bit signal at a predetermined time after a change in an address signal. Thus, regardless of whether or not a time at which the logical level of the bit signal of the sense amplifying circuit is settled coincides, the influence is not exerted on the operation of the subsequent error correcting circuit. As a result, it is possible to prevent the appearance of a hazard in the output data and, accordingly, to realize a perfect ECC relief, while increasing a reliability in the reading operation as a device.

Analysis of mismatch noise in randomly interleaved ADC system

Abstract: Time interleaved A/D converters (ADC) can be used to increase the sample rate of an ADC system. However, a problem with time interleaved ADC is that distortion is introduced in the output signal due to various mismatch errors between the ADC. One way to decrease the impact of the mismatch errors is to introduce additional ADC in the interleaved structure and randomly select an ADC at each sample instance. The periodicity of the errors is then removed and the spurious distortion is changed to a more noiselike distortion, spread over the whole spectrum. In this paper, a probabilistic model of the randomly interleaved ADC system is presented. The noise spectrum caused by gain errors is also analyzed.

Digital to analog converter utilizing pulse width modulation

Abstract: A pulse width digital to analog converter is constructed which provides an output clock rate that is a multiple of the input sampling rate. In one embodiment a latch is used to store N-bit digital word representing the analog signal value to be generated. (N-K) of the most significant bits are stored in a counter which decrements its count in response to a clock signal. A plurality of least significant bits of said digital word stored in said latch are applied to a logic circuit. A ring counter is utilized to indicate which section of the output signal is currently being generated. The plurality of the least significant bits of the digital word stored in the latch, together with the output signals from the ring counter, are applied to said logic circuit, and the transition of the output signal of the digital to analog converter from a logical one to a logical zero is delayed, when required, to provide a slightly increased output pulse width in response to said plurality of least significant bits of said digital word, thereby maintaining or even increasing the resolution of the system.