Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

Method and apparatus for utilizing a data processing system for multi-level data communications providing self-clocking

Abstract: A method and apparatus utilizing a data processing system are disclosed for multi-level data communication providing self-clocking. A first digital signal is input which includes a series of digital bits. One of a plurality of output levels is associated with each group of data bits for each of the plurality of the digital bits included within the first digital signal. A particular output level is associated with a clock output level. An output signal is generate which includes a transmission of the output level for each of the groups of digital bits and includes multiple transmissions of the clock output level, where a clock output level is transmitted after each transmission of an output level for each of the groups of digital bits.

Pipeline ADC digital dithering for increased digital calibration resolution

Abstract: An pipeline analog-to-digital converter (ADC) is provided that is capable of applying calibration at a resolution greater than the resolution of a digital output signal provided by the ADC. The ADC includes a calibration component adapted to apply calibration bits to digital output bits generated by stages of the pipeline and corresponding to samples of an analog input signal. The ADC also includes a random number generator that provides at least one random bit having a sub-LSB bit weight. The calibration bits and the at least one random bit are applied as a dither to the digital output bits such that, on average, the digital output signal provided by the ADC is calibrated at a sub-LSB resolution.

A low-power 10 bit ADC in a 0.25 /spl mu/m CMOS: design considerations and test results

Abstract: This paper presents the design and test of a low power analog-to-digital converter (ADC) implemented in a commercial 0.25 /spl mu/m CMOS technology. The circuit has been developed to serve as a building block in multichannel data acquisition systems for high energy physics (HEP) applications. Therefore, medium resolution (10 bits), very low power consumption, and high modularity are the key features of the design. In HEP experiments, the resistance of the electronics to the ionizing radiation is often a primary issue. Hence, the ADC has been laid out using a radiation-tolerant approach. The test results show that the chip operates as a full 10-bit converter up to a clock frequency of 30 MHz. No degradation in performance has been measured after a total dose of 10 Mrd (SiO/sub 2/).

A 10-bit 50-MS/s SAR ADC with techniques for relaxing the requirement on driving capability of reference voltage buffers

Abstract: A high speed successive approximation (SAR) ADC requires reference voltage buffers with high driving capability. Moreover, the power consumption of the reference buffers is usually several times larger than that of the SAR ADC itself. Three techniques are adopted to mitigate the requirement on driving capability of reference voltage buffers for SAR ADCs. A 10b 50MS/s ADC based on the proposed techniques is presented. The prototype ADC was fabricated in 40nm LP 1P7M CMOS technology. It consumes 0.47 mW at 50 MS/s from 1.1V supply voltage and achieves ENOB of 9.18-bit and figure of merit (FoM) of 16 fJ/conversion-step. The active area is 0.0114 mm2.

Two stage analoge-to-digital converter having unique fine encoding circuitry

Abstract: An analog to digital converter for the conversion of an analog input signal to a digital output code of n bits has a plurality of voltage references created in a voltage reference generator that divides the total range of voltage of the conversion input into increments of voltage equal to the smallest increment of resolution. The n bits of digital output are divided into most significant bits and least significant bits. The most significant bits are encoded from a set of digital signals that are formed in a set of coarse comparators, that compare the analog input signal with a subset of the voltage references representing the coarse range. The digital code that is the output of the coarse comparators is used to determine the selection of the subset of the plurality of the voltage references that are the fine voltage references. The least significant bits are encoded from a set of digital signals that are formed in a set of fine comparators that compare the analog input signal to the fine voltage references. The digital codes that form the most significant bits and the least significant bits are corrected encoded in an output encoder to form the digital output word.