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Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.


Papers
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Proceedings ArticleDOI
06 Mar 2014
TL;DR: This paper presents a 15b 48MS/s zero-crossing-based pipeline ADC that achieves low power consumption of 99fJ/step and high linearity performance of 73.1dB at Nyquist, demonstrating state-of-the-art FoM for thermal-noise-limited designs of 165.1 dB.
Abstract: Pipeline ADCs have traditionally served as a general-purpose architecture for high-speed and high-resolution applications such as medical and wireless receivers. Recently, achieving the highest levels of linearity with ultra-low power consumption has proven to be extremely challenging using modern CMOS technology with limited headroom. While zero-crossing-based circuits (ZCBC) have proven to be a power-efficient alternative to opamps in pipeline ADCs, performance using zero-crossing techniques have to-date only been demonstrated with ENOB ≤11. This paper presents a 15b 48MS/s zero-crossing-based pipeline ADC that achieves low power consumption of 99fJ/step and high linearity performance of 73.1dB SNDR and >80dB SFDR at Nyquist, demonstrating state-of-the-art FoM for thermal-noise-limited designs of 165.1dB.

21 citations

Patent
07 Jul 2005
TL;DR: In this article, a method of rate control in a video encoder includes performing a first encoding step to encode macroblocks of a current frame by utilizing a first quantization parameter to generate a residual signal for the current frame; estimating a number of header bits for each macroblock mode to estimate a total number of headers for each frame, estimating an available number of texture bits according to the total header bits, and then determining a second quantization parameters according to estimated available amount of textures bits.
Abstract: A method of rate control in a video encoder includes performing a first encoding step to encode macroblocks of a current frame by utilizing a first quantization parameter to thereby generate a residual signal for the current frame; estimating a number of header bits for each macroblock mode to thereby estimate a total number of header bits for the current frame; estimating an available number of texture bits according to the total number of header bits for the current frame; determining a second quantization parameter according to the estimated available number of texture bits; and performing a second encoding step to encode the residual signal for the current frame by utilizing the second quantization parameter.

21 citations

01 Jan 2008
TL;DR: In this paper, an all-optical analog-to-digital conversion utilizing inherent multi-wavelength phase shift in lithium niobate phase modulator is proposed, which is a simple realization of the phase shift and high stability.
Abstract: All-optical analog-to-digital conversion utilizing inherent multiwavelength phase shift in lithium niobate phase modulator is proposed. In the experimental demonstration, a wavelength-tunable continuous-wave laser diode and a lithium niobate phase modulator are used to quantize the sinusoidal tone electrical analog signal. Using 16 different wavelengths, an effective number of bits of 4.3-bit has been obtained after software sampling measurement. Benefits of the presented approach in this letter are its simple realization of the phase shift and high stability. Index Terms—Analog-to-digital conversion, phase modulation, photonic analog-to-digital converter (ADC), photonic sampling.

21 citations

Journal ArticleDOI
TL;DR: In this paper, an nth-order multi-bit delta-sigma (ΣΔ) ADC using a successive approximation register (SAR) quantiser is proposed, which can be implemented as a bandpass ADC.
Abstract: An nth-order multi-bit delta-sigma (ΣΔ) analogue-to-digital converter (ADC) using a successive approximation register (SAR) quantiser is proposed. By exploiting the residue voltage of a multi-bit SAR ADC, the proposed ADC performs as an nth-order noise shaping converter with only one opamp and removes the need for a feedback multi-bit DAC. In addition, the proposed architecture is very reconfigurable and can be implemented as a bandpass ADC.

21 citations

Patent
04 Mar 1998
TL;DR: In this paper, an analog successive approximation (SAR) analog-to-digital converter (ADC) is proposed that utilizes N comparators for N bits of output and does not require a clock system, control logic, decode logic, or thermometer to binary decode circuitry.
Abstract: An analog successive approximation (SAR) analog-to-digital converter (ADC) is disclosed that is a compromise between a SAR ADC implementation and a fully parallel thermometer-to-binary ADC. The analog SAR ADC utilizes N comparators for N bits of output and does not require a clock system, control logic, decode logic, or thermometer-to-binary decode circuitry. Conversion speed is determined by the comparator rate, and the comparator outputs may be used directly as the ADC outputs. The analog SAR ADC disclosed is a low complexity, low-precision analog-to-digital converter (ADC) that may be used to digitize phone line status information so that it may be communicated across a isolation barrier as digital information.

21 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202361
2022143
202196
2020147
2019149
2018147