Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

3.1 A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion

Abstract: Giga-sample ADCs targeting high performance communication applications such as direct-RF sampling all rely on some form of residue amplification to minimize the number of interleaved channels and meet demanding specifications. Despite architectural efforts to reduce the total number of amplifiers in the system, the challenges associated with designing them for high bandwidth and linearity has limited reported power efficiencies [1]. In this work, we show that ring amplification [2] can overcome this longstanding bottleneck. In an architecture using 36 ringamps, the 3.2GS/s ADC consuming 61.3mW has a Nyquist SNDR of 61.7dB, SFDR of 73.3dB, Walden FoM of 19.2fJ/conv-step, and Schreier FoM of 165.9dB. Furthermore, we demonstrate a general technique whereby the signal-to-distortion ratio (SDR) of any amplifier in the system can be independently monitored in the background with an analog hardware overhead of only one comparator.

A 1-V 9.8-ENOB 100-kS/s single-ended SAR ADC with symmetrical DAC switching technique for neural signal acquisition

Abstract: This paper reports a high-performance low-power and area-efficient single-ended SAR ADC for neural signal acquisition. The proposed 10-bit ADC features a novel symmetrical DAC switching technique that resolves the signal-dependent comparator offset voltage problem in conventional single-ended SAR ADCs, and improves the ADC's ENOB. Combined with an existing LSB single-sided switching method, the proposed switching scheme reduces DAC switching energy by 92% and capacitor array area by 50%. Besides, the proposed ADC also eliminates the need for any power consuming Vcm generation circuit, making it more suitable for low-power System-on-Chip (SoC) integration. The 10-bit prototype ADC is fabricated in a standard 0.18-um CMOS technology. Operating at 1.0 V power supply and 100 kS/s, the proposed ADC achieves 58.83 dB SNDR and 63.6 dB SFDR for a 49.06 kHz input signal. The maximum ENOB is 9.8-bit for low frequency input signal; and the minimum ENOB is 9.48-bit at the Nyquist input frequency. The average power consumption is 1.72 μW and the fig re-of-merit (FoM) is 24.1 fJ/conversion-step.

Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC

Abstract: This paper proposes a linearity calibration algorithm of a capacitive digital-to-analog converter (CDAC) for successive approximation register (SAR) analog-to-digital converters (ADCs) based on a normalized-full-scale of the DAC. Since the capacitor weight errors are represented as the difference between the real and ideal weights with respect to the normalized-full-scale, the calibrated digital representation of CDAC does not have gain error. A model of a 14-bit-format SAR ADC with a segmented CDAC by a bridge capacitor is simulated to demonstrate the performance of the proposed calibration algorithm. The effective number of bits (ENOB) and spurious-free dynamic range (SFDR) of the 14-bit-format ADC model are improved to 13.2 bits and 94.0 dB from 8.4 bits and 54.8 dB, respectively, at a standard deviation of a unit capacitor of 2%. The gain-error-free characteristic of the proposed linearity calibration algorithm is verified with a 2-channel time-interleaved (TI) SAR ADC model.

Pipelined analog-to-digital converter and method of analog-to-digital conversion

Abstract: A pipelined analog-to-digital converter (ADC) has a multistage structure, and the pipelined ADC includes a plurality of stages that form the multistage structure. Each of the stages includes a sample-and-hold (S/H) circuit, a flash ADC, and a digital-to-analog converter (DAC). The S/H circuit converts an analog input signal to a digital signal. The flash ADC detects a digital bit corresponding to the analog input signal. The DAC converts the digital signal to an analog signal, and amplifies a residue signal, which is a difference between the input analog signal and the converted analog signal, that is provided as an analog input signal of the next stage.

A 5.8 nW 9.1-ENOB 1-kS/s Local Asynchronous Successive Approximation Register ADC for Implantable Medical Device

Abstract: This brief presents a 10-bits successive approximation register analog-to-digital converter (ADC) with a sampling rate of 1 kS/s for implantable medical devices. This ADC is implemented in a 65-nm CMOS process in which leakage current will be a key design parameter. It imposes the highest degree of simplicity in the design of the ADCs architecture. Thus, the transistor count is minimized, which reduces not only the active power, but also the number of leakage sources. The modified top-plate V cm -based switching offers energy efficient switching at the capacitive-DAC (CDAC) and uses simple control logic. In addition, the proposed asymmetrical metal-oxide-metal capacitor reduces the size of the CDAC by 90% for a given gain error. Furthermore, the input referred offset voltage of the dynamic comparator can be improved by the top-plate V cm -based switching method at system level without using any additional transistor. The other building blocks are also simplified for lower power consumption. This ADC occupies an area of 0.046 mm 2 . At 0.9 V and 1 kS/s, the 10-bits ADC consumes 5.8 nW, in which, 2.34 nW is contributed by leakage power consumption. The ADC achieves 9.1-ENOB and an energy efficiency of 10.94-fJ/conversion step.