Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

Compression of the ECG by Prediction or Interpolation and Entropy Encoding

Abstract: Compression of digital electrocardiogram (ECG) signals is desirable for two reasons: economic use of storage space for data bases and reduction of the data transmission rate for compatibility with telephone lines. In a sample of 220 Frank4ead ECG's the removal of signal redundancy by second-order prediction or interpolation with subsequent entropy encoding of the respective residual errors was investigated. At the sampling rate of 200 Hz, interpolation provided a 6 dB smaller residual error variance than prediction. A near-optimal value for the interpolation coefficients is 0.5, permitting simple implementation of the algorithm and requiring a word length for arithmetic processing of only 2 bits in extent of the signal precision. For linear prediction, the effects of occasional transmission errors decay exponentially, whereas for interpolation they do not, necessitating error control in certain applications. Encoding of the interpolation errors by a Huffman code truncated to ±5 quantization levels of 30 ?V, required an average word length of 2.21 bits/sample (upper 96 percentile 3 bits/sample), resulting in data transmission rates of 1327 bits/s (1800 bits/s) for three simultaneous leads sampled at the rate of 200 Hz. Thus, compared with the original signal of 8 bit samples at 500 Hz, the average compression is 9:1. Encoding of the prediction errors required an average wordlength of 2.67 bits/sample with a 96 percentile of 5.5 bits/sample, making this method less suitable for synchronous transmission.

A 4-GS/s 4-bit Flash ADC in 0.18- $\mu{\hbox {m}}$ CMOS

Abstract: A 4-bit noninterleaved flash ADC implemented in 0.18-mum digital CMOS achieves a sampling rate of 4 GS/s. A 32 mum by 32 mum, on-chip differential inductor in each comparator extends the sampling rate without an increase in power consumption. A combination of DAC trimming and comparator redundancy reduces the measured DNL and INL to less than 0.15 LSB and 0.24 LSB, respectively. The measured ENOB with a 100 MHz full-power input is 3.84 bits and 3.48 bits, at 3 GS/s and 4GS/s, respectively. The ADC achieves a bit error rate of less than 10-11 at 4 GS/s.

Digital encoder with dynamic quantization bit allocation

Abstract: A digital encoder for compressing a digital input signal derived from an analog signal to reduce the number of bits required to represent the analog signal with low quantizing noise. In the encoder, a digital input signal representing the analog signal is divided into three frequency ranges. The digital signal in each of the three frequency ranges is divided in time into frames, the time duration of which may be adaptively varied. The frames are orthogonally transformed into spectral coefficients, which are grouped into critical bands. The total number of bits available for quantizing the spectral coefficients is allocated among the critical bands. In a first embodiment and a second embodiment, fixed bits are allocated among the critical bands according to a selected one of a plurality of predetermined bit allocation patterns and variable bits are allocated among the critical bands according to the energy in the critical bands. In the first embodiment, the apportionment between fixed bits and variable bits is fixed. In a second embodiment, the apportionment between fixed bits and variable bits is varied according to the smoothness of the spectrum of the input signal. In a third embodiment, bits are allocated among the critical bands according to a noise shaping factor that is varied according to the smoothness of the spectrum of the input signal. All three embodiments give low quantizing noise with both broad spectrum signals and highly tonal signals.

A Compressed Sensing Parameter Extraction Platform for Radar Pulse Signal Acquisition

Abstract: In this paper we present a complete (hardware/ software) sub-Nyquist rate (× 13) wideband signal acquisition chain capable of acquiring radar pulse parameters in an instantaneous bandwidth spanning 100 MHz-2.5 GHz with the equivalent of 8 effective number of bits (ENOB) digitizing performance. The approach is based on the alternative sensing-paradigm of compressed sensing (CS). The hardware platform features a fully-integrated CS receiver architecture named the random-modulation preintegrator (RMPI) fabricated in Northrop Grumman's 450 nm InP HBT bipolar technology. The software back-end consists of a novel CS parameter recovery algorithm which extracts information about the signal without performing full time-domain signal reconstruction. This approach significantly reduces the computational overhead involved in retrieving desired information which demonstrates an avenue toward employing CS techniques in power-constrained real-time applications. The developed techniques are validated on CS samples physically measured by the fabricated RMPI and measurement results are presented. The parameter estimation algorithms are described in detail and a complete description of the physical hardware is given.

Digitally Calibrated 768-kS/s 10-b Minimum-Size SAR ADC Array With Dithering

Abstract: Array sensors require a high-performance analog-to-digital converter (ADC) array with small area and low power. Successive-approximation register (SAR) ADC has good potential for ADC array due to its simple analog circuits. However, SAR ADCs with 10-b resolution and higher normally need a large capacitor array due to the stringent matching requirement. The large capacitor array also limits the ADC dynamic performance. The capacitor mismatch has been compensated by analog calibration techniques. In this work, a novel digital calibration method is developed for SAR ADC based on dithering. With dithering, weights of most significant bit (MSB) capacitors can be measured accurately so that very small capacitors can be used in the SAR ADC due to the relaxed matching requirement. A modified bit-cycling procedure is developed to avoid the code gaps caused by capacitor dithering. This calibration technique requires no analog calibration overhead and simple digital decoders. The technique is implemented in an ADC array design including 256 SAR ADCs for a high-speed CMOS imaging sensor in a 0.18-μm CMOS process. The 10-b SAR ADC is designed with the minimum capacitor array size in the process. A single SAR ADC only occupies 15 μm × 710 μm. Sampling at 768 kS/s, peak DNL and peak INL of the original ADCs averaged across the array are 0.82 least significant bit (LSB) and 3.85 LSB, respectively. For a signal close to the Nyquist frequency, original ADCs have 7.96-b average ENOB. After calibration with dithering, ADCs have 0.55-LSB peak DNL and 0.77-LSB peak INL averaged across the array. The average ENOB improves to 9.83 b. Compared with the benchmark 10-b SAR ADCs, this design is the most area-efficient design. In this work, the calibration decoders are implemented off-chip. With a sample-and-hold amplifier, the calibration method can run in the background.