Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

Data Communication Module Providing Fault Tolerance and Increased Stability

Abstract: A module for transmitting sets of data bits to another module via a communication bus using dual-rail encoding is provided that has a reduced switching activity. The module comprises bus invert coding means adapted to compare a set of data bits with a preceding set of data bits to determine an indication of the number of transitions required to transmit the set of data bits; invert the set of data bits prior to transmission if it is determined that the number of transitions required to transmit the set of data bits is greater than half the total number of bits in the set of data bits; and provide an indication of whether the set of data bits has been inverted; the module also comprising means adapted to generate respective copies of the data bits in the set of data bits; and means adapted to transmit to the other module, via the communication bus, the set of data bits, their respective copies and the indication of whether the set of data bits has been inverted.

Design of CMOS sampling switch for ultra-low power ADCs in biomedical applications

Abstract: This paper deals with the design of CMOS sampling switch for ultra-low power analog-to-digital converters (ADC) in biomedical applications. General switch design constraints are analyzed, among which the voltage droop due to the subthreshold leakage current constitutes the major error source for low-speed sampling circuits. Based on the analyses, a CMOS sampling switch with leakagereduction has been designed for a 10-bit 1-kS/s successive approximation (SA) ADC in a standard 130 nm CMOS process. Post-layout simulation shows that the ADC with the proposed switch offers an effective number of bits (ENOB) of 9.5 while consuming only 64 nW.

Zero-Crossing-Based Ultra-Low-Power A/D Converters

Abstract: Since the first demonstration of a comparator-based switched-capacitor circuit, analog-to-digital (A/D) converters based on virtual ground detection have made steady and significant progress. Comparators have been replaced by zero-crossing detectors, leading to the development of zero-crossing based circuits for faster speed and lower power. All facets of performance including the sampling rate, effective number of bits, noise floor, and figure-of-merit have improved substantially. This paper focuses on recent implementations of zero-crossing based A/D converters and discusses the technical issues unique to these A/D converters as well as solutions that have been developed to improve their performance and practicality. A series of prototype designs whose performance ranges from 8 bit, 200 MS/s to 12 bit, 50 MS/s are described. The ultimate low power potentials of these A/D converters are compared with various different types of complementary metal-oxide-semiconductor A/D converters from a fundamental thermal noise standpoint.

Compressing signals using serially-concatenated accumulate codes

Abstract: A method compresses a set of correlated signals by first converting each signal to a sequence of integers, which are further organized as a set of bit-planes. This can be done by signal transformation and quantization. An inverse accumulator is applied to each bit-plane to produce a bit-plane of shifted bits, which are permuted according to a predetermined permutation to produce bit-planes of permuted bits. Each bit-plane of permuted bits is partitioned into a set of blocks of bits. Syndrome bits are generated for each block of bits according to a rate-adaptive base code. Subsequently, the syndrome bits can be decompressed in a decoder to recover the original correlated signals. For each bit-plane of the corresponding signal, a bit probability estimate is generated. Then, the bit-plane is reconstructed using the syndrome bits and the bit probability estimate. The sequence of integers corresponding to all of the bit-planes can then be reconstructed from the bit probability estimates, and the original signal can be recovered from the sequences of integers using an inverse quantization and inverse transform.

Low roundoff noise digital filter

Abstract: An error feedback circuit is employed in a digital filter to significantly lower noise in the output by feeding back the least significant (roundoff) output bits of the quantizer rather than throwing these bits away as is done in the prior art. The feedback circuit for accomplishing this end result includes a digital delay circuit which receives the roundoff bits and delays these bits for a sampling sequence (Z -1 ) (as is also done for the rounded bits), a multiplier which multiplies the output of the delay circuit by a predetermined integer and an adder which subtracts the output of the multiplier from the delayed filtered digital output signal which has been multiplied by a predetermined constant.