Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC.

Abstract: This paper presents a sub-ranging 6-way time-interleaved pipelined-SAR ADC that achieves 900MS/s and 9.3 ENOB in 65nm CMOS. The architecture optimization is based on a pipelined-SAR structure that obtains high-speed with an optimized number of channels, thus leading to relaxed calibration with higher efficiency in power and area consumption. The proposed channel-selection-embedded bootstrap performs sampling instants synchronization without additional components, thus effectively suppressing the spurs from time skews below -65 dBFS. The mismatch errors due to offset and gain are all solved on-chip, whose spurs are suppressed below -67 dBFS. The prototype achieves 66 dB SFDR and 51.5 dB SNDR with a Nyquist input exhibiting a FoM of 56 fJ/conv.step.

Analog-to-digital converter with digital signal processing functionality to emulate many different sample frequencies, resolutions, and architectures

Abstract: A system for emulating characteristics of a plurality of analog-to-digital converter (ADC) architectures in the conversion of an analog signal to a digital signal. The system comprises a flash ADC for sampling the analog signal and outputting a digital representation of a sample of the analog signal, a digital-to-analog converter (DAC) for supplying the reference values to the flash ADC, and a digital signal processor (DSP) for processing the digital representation of the sample and outputting the digital signal. The digital representation is based on a comparison of the sample to reference values and comprising a number of bits of resolution. The DSP is configured to send a modifiable control signal defining the reference values to the DAC.

Method for providing an improved run-length encoding algorithm for data compression

Abstract: The present invention provides an improved method for encoding a plurality of bit sequences. The present invention includes reading a bit sequence; determining a minimum number of bits for a repeat factor for the bit sequence, where the minimum number of bits is variable; and encoding the bit sequence using the repeat factor. The method provides an improved run-length encoding algorithm by using a strategy where the number of bits used to represent the repeat factor (RF) varies for each individual sequence of equal-valued bits. Rather than conventionally representing the RF by any predetermined and fixed number of bits, the RF of the present invention is represented by the minimum number of bits to binary-encode that repeat factor as an unsigned integer. The RF for each individual bit sequence is represented using only the minimum number of bits necessary, regardless of any previous or following RF.

A 4.1mW, 12-bit ENOB, 5MHz BW, VCO-based ADC with on-chip deterministic digital background calibration in 90nm CMOS

Abstract: A deterministic digital background calibration technique to correct non-linearity in VCO-based ADCs is presented. Implemented in 90nm CMOS process, on-chip calibration improves SFDR of the prototype ADC from 46dB to more than 83dB. The ADC consumes 4.1mW power and achieves 73.9dB SNDR in 5MHz signal bandwidth.

Failure analysis system of semiconductor memory device

Abstract: In failure analysis method of a semiconductor memory device, an absolute value of a position difference between two fail bits of a two-dimensional bit map is calculated while a histogram corresponding to the absolute value of the position difference is updated. The bit map indicates a map of fail bits and each fail bit corresponds to a fail memory cell. The above calculation is repeated to all combinations of two of the fail bits in the bit map. Then, an expectation function value is calculated for each of values from the histograms and the number of the fail bits. Finally, whether the fail bits has regularity or irregularity for each value is determined based on the calculated expectation function value for the value.