Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

Bus encoding/decoding apparatus and method

Abstract: A bus encoding/decoding apparatus and method for a low power digital signal processor (DSP), which uses a narrow data bus, is provided. The apparatus for encoding n bits of data of a data bus, includes a conditional inverting unit for inverting each of (n−1) lower bits of n data when the most significant bit of the n bits of data is 1, a storage unit for storing the last n bits of data which is output to the bus, and a first exclusive OR operating unit for performing a bitwise exclusive OR operation on the lower (n−1) bits or data, which has been inverted by the conditional inverting unit, and the lower (n−1) bits of the n data, which has been stored in the storage unit, wherein the most significant bit of the n bits of data and (n−1) bits of data, which is obtained as the result of the bitwise exclusive OR operation performed by the first exclusive OR operating unit, are output. Accordingly, interface problems with a core and overhead for an additional circuit can be reduced by removing the additional circuit for determining whether to invert data and an extra line, which are used in the conventional BI and BITS coding methods, thereby decreasing the power consumption and the area of a chip.

Virtual buffer size management system for the transmission of blocks of data bits in an HS-DSCH downlink channel of a mobile communications network

Abstract: A first rate matching stage matches a number of input bits coming from a transport channel including a high-speed downlink shared channel (HS-DSCH) of a block of data bits to be transmitted from a base station of a communications network to one or more pieces of user equipment (UE) to a selected number of intermediate bits as determined by the buffer size management system. A virtual buffer stores the selected number of intermediate bits. A second rate matching stage matches the selected number of intermediate bits to a number of output bits equal to a maximum number of bits that is guaranteed to be transmitted by a set of high-speed physical downlink shared channels (HS-PDSCH) associated with the transport channel in a given time interval without adding bits.

Capacitive folding circuit for use in a folding/interpolating analog-to-digital converter

Abstract: An M-bit folding/interpolating analog-to-digital converter (ADC) circuit, comprising a reference voltage generator, a converter, an interpolator, an amplifying stage, a comparator, and an encoder. The converter has an amplifier that receives at least one of a plurality of first reference voltage signals and outputs a plurality of coarse bits. The converter also has N-number of folding blocks, which output a plurality of folded signals. Each folding block comprises a plurality of capacitors, a differential amplifier and a feedback element. The folded signals output by the converter are then interpolated, amplified, compared and output as a plurality of fine bits. The encoder receives the coarse and fine bits and outputs the digital signal.

A Design of 8 fJ/Conversion-Step 10-bit 8MS/s Low Power Asynchronous SAR ADC for IEEE 802.15.1 IoT Sensor Based Applications

Abstract: An energy efficient, low-power 10-bit asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter with the sampling frequency of 8 MS/s is presented for IEEE 802.15.1 IoT sensor based applications. An improved common mode charge redistribution algorithm is proposed for binary weighted SAR ADC. The proposed method uses available common mode voltage (VCM) level for SAR ADC conversion, and this method reduces the switching power by more than 12% without any additional DAC driver as compared to merged capacitor switching (MCS). Mathematical analysis of the proposed switching scheme results in the lower or equal power consumption for every digital code as compared to MCS. A two stage dynamic latched comparator with adaptive power control (APC) technique is used to optimize the overall efficiency. Furthermore, to minimize the digital part power consumption, a modified asynchronous SAR logic with digitally controlled delay cells is proposed. High efficiency with low power consumption makes it suitable for low power devices especially for IEEE 802.15.1 IoT sensor based applications. The proposed prototype is implemented using 1P6M 55 nm complementary metal-oxide-semiconductor (CMOS) technology. The measurement results that the proposed circuit achieves are 9.3 effective number of bits (ENOB) with signal-to-noise and distortion ratio (SNDR) of 58.05 dB at a sampling rate of 8 MS/s. The power consumption of SAR ADC is $45~\mu \text{W}$ when operated at 1 V power supply.

Characterizing the performance of a high-speed adc for the sma digital backend

Abstract: We report on tests of a 5 Gs/s analog-to-digital converter (ADC) used in the new Submillimeter Array (SMA) Digital Backend (DBE). The ADC is e2v EV8AQ160, with 8-bit resolution and 4 interleaved cores, operated in single-channel mode. We measured the frequency response, Signal to Noise and Distortion (SINAD), Spurious Free Dynamic Range (SFDR), Noise Power Ratio and intermodulation distortion over the bandwidth of 2.25 GHz. The performance of this ADC is found to be adequate for our application in the SMA DBE. We describe the procedure of aligning the four cores for adjustments of offset, gain and phase parameters which improve the performance of the ADC, particularly in SINAD and SFDR.