Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

Memory implemented error detection and correction code using memory modules

Abstract: A method and apparatus for performing digital signal error detection and correction through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of "1" or a low value of "0". At least one address parity bit is then generated from each group and used in checking the integrity of data received. Errors are corrected and detected through assignment of data bits to different modules in a memory of a computer system having symbols which are b bits in length.

Impact of Optical Nonlinearity on Performance of Photonic Time-Stretch Analog-to-Digital Converter

Abstract: Wideband real-time analog-to-digital converters are the central tools in waveform analyzers, communication systems, and radar technology. Photonic time-stretch analog-to-digital converters (TSADCs) utilize a broadband optical source and an optical link to extend the capabilities of real-time digitizers, allowing acquisition of wideband radio frequency (RF) signals with high resolution. In the TSADC, it is desirable to improve the signal-to-noise-and-distortion ratio and effective number of bits by increasing the optical power. Here, we numerically evaluate the impact of optical nonlinearity on TSADC performance. It is demonstrated that the optical nonlinearity can impose an upper limit on the effective number of bits and that the RF bandwidth limitation due to dispersion penalty depends on optical power. The trends presented here can also be applied to other optical links in which optical nonlinearity and dispersion are significant.

An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS

Abstract: This paper demonstrates an asynchronous successive-approximation-register (SAR) analog-to-digital converter (ADC) architecture with an embedded passive gain technique for low-power and high-speed operation. The proposed passive gain technique relaxes the noise requirement of the comparator and reuses the existing capacitor DAC in SAR for minimal overhead. An additional time-out scheme is adopted to advance the SAR conversion whenever the comparator takes longer time to resolve, which improves the overall conversion rate. To prove the concept, an 11-bit ADC prototype was fabricated in 65 nm CMOS technology. The prototype measured a peak effective number of bits (ENOB) of 10.2 and a spurious-free dynamic range (SFDR) of 75.2 dB at a 95-MS/s sampling rate with 1.36-mW power consumption from a 1.1 V supply. The measured static differential nonlinearity (DNL) and integral nonlinearity (INL) were less than ± 0.84 LSB with a differential input swing of 1.6 $\mathbf{V}_{\boldsymbol{pp}}$ .

A 12-bit SAR ADC With a DAC-Configurable Window Switching Scheme

Abstract: This paper presents a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) that uses a digital-to-analog converter (DAC) configurable window switching technique. By reusing the capacitors in the DAC, the proposed window switching scheme yields window boundaries to determine whether the input is located within the window, and thus avoid unnecessary capacitor switching. The proposed window SAR ADC improves the conversion efficiency and ADC linearity. A qualitative analysis of prior window switching schemes is presented to elaborate for various applications. A low-input capacitance of 1 pF was adopted to relax the input and reference buffers. A prototype ADC was implemented in 180-nm CMOS occupying an active area of 0.1 mm2. At 20 MS/s, it consumes a total power of 1.22 mW from a 1.5-V supply. The measured peak signal-to-noise and distortion ratio and spurious-free dynamic range were 61.7 and 79 dB, respectively. At the Nyquist rate, the measured effective number of bits (ENOB) was 9.53, equivalent to a figure-of-merit (FOM) of 83 fJ/conversion-step. In low-power mode (100 kS/s), it consumed a total power of $1.5~\mu \text{W}$ from a 0.7-V supply. At the Nyquist rate, the measured ENOB was 9.82, equivalent to a FOM of 16.6 fJ/conversion step.

Comparator with built-in reference voltage generation and split-ROM encoder for a high-speed flash ADC

Abstract: Two circuit techniques for performance enhancement of high-speed flash ADCs are proposed. A calibration-intensive dynamic comparator features an improved built-in reference voltage generation scheme to alleviate the issue of kickback noise, and a proper reset function to clean the memory effect due to the dielectric relaxation in the capacitors, yielding better static and dynamic linearity performances. The second is a split-ROM encoder, which halves the signaling path to lower the parasitics, while boosting the back-end processing speed with small power. The feasibility of them is demonstrated via a 5-bit flash ADC designed in 65nm CMOS. With 3.69mW of power, the ADC operated at 2GS/s exhibits an ENOB of >4.5 bits up to an ERBW of 3.6GHz. The DNL and INL are within +0.091/−0.071 and +0.066/−0.062 LSB, respectively.