Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

A 43.6-dB SNDR 1-GS/s single-channel SAR ADC using coarse and fine comparators with background comparator offset calibration

Abstract: A 43.6dB-SNDR 1-GS/s 8-bit single-channel successive-approximation-register (SAR) analog-to-digital converter (ADC) using coarse and fine comparators with fully background comparator offset calibration is presented. Low-power coarse comparators and low-noise fine comparators are both employed to improve the comparator power efficiency. Non-binary digital-to-analog converter (DAC) with redundancy is employed to tolerate possible errors in the most-significant-bit (MSB) decisions. A novel comparator offset calibration scheme is proposed to remove the offsets between the different comparators, without slowing down the speed of the SAR conversion. The prototype ADC is implemented in a 28 nm CMOS technology and achieves an ENOB of 6.95 (43.6-dB SNDR) near Nyquist frequency while consuming 3.2 mW, translating into an FOM of 25.87 fJ/conversion-step. To the best of our knowledge, this ADC achieved the highest SNDR among all single-channel SAR ADCs reported that operate above 1GS/s.

Output compensating system

Abstract: A system for compensating for variations in an output consisting of many components that show variations, comprising a memory for storing the compensation value for each component, an analog-to-digital converter for converting the output into several bits of digital output, a multiplier for multiplying the value of the high order bits of the digital output by the compensation value, and a subtracter for subtracting the output of the multiplier from the value of the low order bits. Instead of using the multiplier, the order of the value of the high order bits can be lowered down to that of the value of the low order bits, and the obtained value can be subtracted from the low order bits the number of times indicated by the compensation value.

Multi-bit error correction system

Abstract: An improved multi-bit error correction system. The inventive error correcting system performs a fast error correction operation on individual bits within multi-bit modules. In a specific implementation, the invention uses Hamming codes and divides an n times m bit data word into m modules, with each module having n bits. Next, the ith bits of each module are combined to form a set of parity bits. Syndrome bits are generated from the parity bits and used to locate errors in the bits and provide an indication of same. Finally, errors in the bits are corrected in a conventional manner to provide corrected data bits.

Duty cycle corrector for a random number generator

Abstract: A method and apparatus for producing a corrected bit stream from a random bit stream output by a random bit source. Sequential pairs of bits in the random bit stream are compared. If both bits in a pair of bits are identical, the output bits are discarded. If both bits in a pair of bits are different, one bit of the pair of bits is taken as the output bit.

Design limitations for superconducting A/D converters

Abstract: This paper reviews the principle of A/D conversion using superconducting quantum interference and describes the results obtained with this technique At an accuracy of four or six bits the design of such converters is straightforward. Higher accuracy requires careful consideration of numerous design constraints including critical current uncertainty, power supply regulation, turn-on-delay, signal line crosstalk, and the threshold curve critical points. The implications of these constraints are analyzed with respect to an example design for an 8-bit converter.