Topic
Effective number of bits
About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.
Papers published on a yearly basis
Papers
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01 Sep 2013
TL;DR: A 10b successive approximation register (SAR) analog-to-digital converter (ADC) that operates at 0.5V supply voltage and supports a flexible differential input dynamic range from 0.4V to 1V is presented.
Abstract: This paper presents a 10b successive approximation register (SAR) analog-to-digital converter (ADC) that operates at 0.5V supply voltage and supports a flexible differential input dynamic range from 0.4V to 1V. The proposed ADC employs a majority vote comparison along with a non-binary architecture to alleviate the effect of comparator noise in scaled input voltage swings. To maximize performance subject to comparator power level constraints, the allocation of votes is optimized for each bit cycle. The prototype, fabricated in 65nm CMOS process, achieves ENOB ranging from 7.1b to 9.1b and FOM from 3.3 to 6.8fJ/conversion step while operating at 250kS/s.
16 citations
19 Feb 1992
TL;DR: A fully differential two-step ADC is described which presents solutions for sample and hold, the DAC, the gain-matching between coarse and fine high performance with low power consumption and small chip area.
Abstract: Most multistep analog-to-digital converter (ADC) architectures presented thus far suffer from poor linearity caused by the sample and hold as well as the internal digital-to-analog converter (DAC). Furthermore, the gain-matching between coarse and fine ADC gives rise to nonmonotonicity. A fully differential two-step ADC is described which presents solutions for sample and hold, the DAC, the gain-matching between coarse and fine high performance with low power consumption and small chip area. >
16 citations
TL;DR: A new filter bank structure used for decomposing a signal into its main spectral components, like signal-to-noise and distortion ratio, signal to noise ratio, total harmonic distortion, and so on, in noncoherent sampling is presented.
Abstract: The aim of this paper is to propose a new spectral analysis method for an on-chip analog-to-digital converter (ADC) dynamic test. ADC characterization by spectral analysis has traditionally been done with discrete Fourier transform. This method imposes restrictions to optimize results; one of these is coherent sampling. Recently, some filter structures have been used for spectral analysis of a sinusoidal signal corrupted by harmonics and noise. In this paper, we present a new filter bank structure used for decomposing a signal into its main spectral components. The main application examined is ADC spectral parameter estimation, like signal-to-noise and distortion ratio, signal to noise ratio, total harmonic distortion, and so on, in noncoherent sampling. Computer simulations are used to demonstrate the performance of the proposed filter bank scheme. This structure is a promising built-in self-test (BIST) approach for ADC ICs.
16 citations
28 Apr 2009
TL;DR: This paper reports a 6-bit 220-MS/s time-interleaving successive approximation register analog-to-digital converter (SAR ADC) for low-power low-cost CMOS integrated systems.
Abstract: This paper reports a 6-bit 220-MS/s time-interleaving successive approximation register analog-to-digital converter (SAR ADC) for low-power low-cost CMOS integrated systems. The major concept of the design is based on the proposed set-and-down capacitor switching method in the DAC capacitor array. Compared to the conventional switching method, the average switching energy is reduced about 81%. At 220-MS/s sampling rate, the measured SNDR and SFDR are 32.62 dB and 48.96 dB respectively. The resultant ENOB is 5.13 bits. The total power consumption is 6.8 mW. Fabricated in TSMC 0.18-µm 1P5M Digital CMOS technology, the ADC only occupies 0.032 mm2 active area.
16 citations
08 Apr 2018
TL;DR: This work presents a 0.6 V analog frontend (AFE) IC consisting of an instrumentation amplifier (IA), a current source (CS) and a SAR ADC that can measure ECG and BioZ simultaneously with a single IA by employing an orthogonal chopping scheme.
Abstract: Simultaneous measurement of Electrocardiogram (ECG) and bio-impedance (BioZ) via disposable health patches is desired for patients suffering from chronic cardiovascular and respiratory diseases. However, a sensing IC must consume ultra-low power under a sub-volt supply to comply with miniaturized and disposable batteries. This work presents a 0.6 V analog frontend (AFE) IC consisting of an instrumentation amplifier (IA), a current source (CS) and a SAR ADC. The AFE can measure ECG and BioZ simultaneously with a single IA by employing an orthogonal chopping scheme. To ensure the IA can tolerate up to 300mVpp DC electrode offset and 400mV pp common-mode (CM) interference, a DC-servo loop (DSL) combined with a common-mode feedforward (CMFF) loop is employed. A buffer-assisted scheme boosts the IA's input impedance by 7x to 140MΩ at 10Hz. To improve the BioZ sensitivity, the CG utilizes dynamic element matching to reduce the 1/f noise of the output current, leading to 35mΩ/√Hz BioZ sensitivity down to 1Hz. The ADC shows a 9.7b ENOB when sampled at 20ksps. The total power consumption of the AFE is 3.8μW.
16 citations