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Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.


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Proceedings ArticleDOI
01 Jul 2017
TL;DR: This paper proposes the different way of designing standard-cell based flash ADC in order to increase its input dynamic range and includes implementation of 5-bit flash ADC for fully automated digital synthesis.
Abstract: This paper proposes the different way of designing standard-cell based flash ADC in order to increase its input dynamic range. It includes implementation of 5-bit flash ADC for fully automated digital synthesis. The input dynamic range is increased by including 5-input logic gates. The proposed architecture results in Differential Non-Linearity (DNL) of ±0.206 LSB and Integral Non-Linearity (INL) of ± 0.218 LSB range. This standard-cell based flash ADC has Effective Number of Bits (ENOB) of 4.78 bits at the sampling frequency of 400 MS/s. The Spurious-Free Dynamic Range (SFDR) of 42.05 dB is achieved at an input frequency of 1.95 MHz.

15 citations

Proceedings ArticleDOI
11 Dec 2002
TL;DR: The design and the implementation of a low power, low voltage 10bit-50MS/s pipeline analog to digital converter (ADC) dedicated to ultrasonic receivers and a digital offset compensation to relax the constraints on the analog circuitry is proposed.
Abstract: This paper concerns the design and the implementation of a low power, low voltage 10bit-50MS/s pipeline analog to digital converter (ADC) dedicated to ultrasonic receivers The ADC is used in the front-end stage to convert the signals coming from the time gain compensator (TGC) of the handheld ultrasonic apparatus The proposed architecture is based on 15 bits per stage pipeline structure followed by a digital offset compensation to relax the constraints on the analog circuitry The converter is implemented in digital CMOS 018 /spl mu/m technology, the circuit occupies an active area of 12 mm/sup 2/, the input differential voltage dynamic range is chosen to be 16 Vpp and the power consumption is found to be 31 mW from 18 V supply

15 citations

Proceedings ArticleDOI
18 Mar 2010
TL;DR: A hybrid CLS-opamp/ZCBC pipelined ADC that incorporates CLS and a low power, small output swing double-cascoded telescopic opamp to achieve very high effective gain and a dynamically biased zero-crossing detector is introduced that increases the power efficiency of ZCBC designs.
Abstract: Scaling in CMOS technologies has made the application of traditional opamp topologies increasingly difficult. In the face of decreasing voltage headroom and intrinsic device gain, designers have employed techniques such as gain-boosting, correlated double sampling , and correlated level-shifting (CLS) [1] to maximize output swing for a given gain specification. Zero-crossing based circuits (ZCBC) remove the opamp altogether and use a comparator and current sources [2], which are more amenable to scaling and have proven capable of high efficiency, as in [3]. However, the open loop nature of ZCBC creates challenges for designs that must reliably track over process, voltage, and temperature. In this paper, we describe a hybrid CLS-opamp/ZCBC pipelined ADC that introduces techniques to improve accuracy, robustness, and power efficiency in scaled technologies. It incorporates CLS and a low power, small output swing double-cascoded telescopic opamp to achieve very high effective gain. A dynamically biased zero-crossing detector (ZCD) is introduced that increases the power efficiency of ZCBC designs.

15 citations

Patent
18 Mar 1991
TL;DR: In this paper, a D/A converter with constant-current output circuits, provided for the n bits of the digital signal, for selectively generating n constant currents on the basis of the n-bits of digital signals, is described.
Abstract: A D/A converter converting a digital signal having n bits (n is an integer) into an analog signal includes constant-current output circuits, provided for the n bits of the digital signal, for selectively generating n constant currents on the basis of the n bits of the digital signals. The n constant currents have mutually different current values with respect to the n bits of the digital signal. The constant-current output circuits have resistance elements respectively provided for the n bits of the digital signal. The resistance elements define the mutually different current values. The D/A converter also includes an output circuit for adding the n constant currents to each other and for outputting the analog signal based on an addition result, and a temperature-dependent voltage generating part for generating a temperature-dependent voltage which changes as a temperature around the D/A converter changes. Further, the D/A converter includes a current compensation part for generating a compensation voltage related to at least one of the resistance elements from the temperature-dependent voltage and for applying the compensation voltage to the one of the resistance elements. The compensation voltage compensates for a temperature-dependent variation in a characteristic of the one of the resistance elements.

15 citations

Proceedings ArticleDOI
25 Oct 2012
TL;DR: A 9-bit 100 MS/s flash-successive approximation register (SAR) analog-to-digital converter (ADC), which is suitable for wireless communication systems, is presented and front-end track-and-hold circuits in the flash ADCs are substituted by dynamic ones to reduce the active area and power consumption.
Abstract: A 9-bit 100 MS/s flash-successive approximation register (SAR) analog-to-digital converter (ADC), which is suitable for wireless communication systems, is presented. To reduce the active area and power consumption, front-end track-and-hold circuits in the flash ADCs are substituted by dynamic ones. A variable delay loop for enhancing dynamic performances is also included in the ADC. The prototype was fabricated using a 45 nm complementary metal-oxide-semiconductor technology with an active area of 0.068 mm2. The differential and integral nonlinearities of the ADC are less than 0.94 and 0.66 LSB, respectively. At a 1.0 V supply and 100 MS/s, the ADC achieves a peak signal-to-noise-distortion ratio and spurious-free dynamic range of 51.94 and 65.87 dB, respectively and consumes 6.1 mW with the internal reference buffer.

15 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202361
2022143
202196
2020147
2019149
2018147