Topic
Effective number of bits
About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.
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07 Mar 2000TL;DR: In this article, a method for decoding a stream of channel bits of a signal relating to a binary channel (21, 30) into a source bit of a binary signal relating with a binary source (40) was proposed.
Abstract: The invention relates to a method of decoding a stream of channel bits of a signal relating to a binary channel (21, 30) into a stream of source bits of a signal relating to a binary source (40). This binary channel comprises a main channel (21) and a secondary channel (30). This secondary channel is embedded in the main channel. In order to correct errors in the stream of secondary channel bits a stream of corrected main channel bits is used. This stream of corrected main channel bits is reconstructed from a stream of corrected source bits (25). The secondary channel can be embedded in the main channel in different manners, e.g. via multi-level coding or via merging-bit coding. The invention further relates to a device for decoding.
15 citations
TL;DR: This paper proposes an adaptive piecewise linear bits estimation model with a tree structure that achieves about the same high performance with a much lower complexity and high self-adaptativity than the bits model derived from training data based on cluster analysis.
15 citations
11 Jun 1991
TL;DR: A novel analog-to-digital converter (ADC) designed to operate without any clocking circuitry, such as a sample-and-hold, is described, resulting in a digital output that is Gray-coded.
Abstract: A novel analog-to-digital converter (ADC) designed to operate without any clocking circuitry, such as a sample-and-hold, is described. The design presented is a first-generation Gray-code algorithmic converter (GA-ADC) with a continuous analog transfer function. The continuous transfer function results in a digital output that is Gray-coded. Performance degrades gracefully as the input exceeds the ADC's maximum sampling rate, enabling one to use a single ADC for a large variety of applications. In addition, the converter has other useful features such as low power dissipation, and high area efficiency. >
15 citations
01 Dec 2012
TL;DR: An 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) is presented and implemented with TSMC 0.18-um CMOS process and makes use of an asynchronous control circuit to internally generate the necessary clock signals to reduce half comparator and digital circuit power consumption.
Abstract: An 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) is presented and implemented with TSMC 0.18-um CMOS process. The SAR ADC makes use of an asynchronous control circuit to internally generate the necessary clock signals to reduce half comparator and digital circuit power consumption. To avoid using a high-frequency clock generator, the proposed ADC uses an asynchronous control circuit to internally generate the necessary clock signals. The dynamic comparator generates the valid signal is the control signal of the sampling switches; it turns on the switches at high potential and turns off the switches at low potential. The average switching energy and total capacitance are reduced. Regarding that, the power consumption can be reduced to "half" by using asynchronous control circuit. Power dissipation is then minimized by optimizing the architecture and by careful design of analog circuitry. Measured results show that the proposed 8-bit SAR ADC consumes 10.3 µW with 1.8-V supply voltage. When sampling at 1.0 MSample/s, the prototype ADC achieves 45.3 dB/56.6 dB peak signal-to-noise-and-distortion ratio (SNDR)/SFDR and an effective number of bits (ENOB) of 7.23 bit. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) are 0.66 LSB and 0.61 LSB, respectively. The core circuitry measures 0.205 (0.57 × 0.36) mm2 and including pads, the chip area occupies only 0.69 (1.03 × 0.67) mm2.
15 citations
TL;DR: In this article, a 5-bit 1.25-GS/s folding flash with a capacitive folding technique is presented, which achieves a folding factor of four and a total power consumption of 595 μW.
Abstract: This paper presents a 5-bit 1.25-GS/s folding flash ADC. The prototype achieves a folding factor of four with a capacitive folding technique that only consumes dynamic power. Incorporated with various calibration schemes, folding errors and the comparator's threshold inaccuracies are corrected, thus allowing a low input capacitance of 80 fF. The design is fabricated using 65-nm digital CMOS technology and occupies 0.007 mm 2. The maximum DNL and INL post calibration are 0.67 and 0.47 LSB, respectively. Measurement results show that the ADC can achieve 1.25 GS/s at 1-V supply with a total power consumption of 595 μW. In addition, it exhibits a mean ENOB of 4.8b at dc among ten chips, which yields an FoM of 17 fJ/conversion-step.
15 citations