Topic
Effective number of bits
About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.
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TL;DR: A low power SAR logic-based resistive sensor readout circuit is proposed, using a high sensitivity thermistor for local temperature measurements and employing time-domain operation to avoid the need for a low-noise front-end voltage amplifier.
Abstract: A low power SAR logic-based resistive sensor readout circuit is proposed. A high sensitivity thermistor is used for local temperature measurements. The need for a low-noise front-end voltage amplifier is avoided by employing time-domain operation. In each operation step the sensor resistance is compared with the value of a reference resistive DAC which is implemented on chip. Therefore no stable, temperature compensated reference voltage is needed for operation. Furthermore the chip is operational with supply voltages ranging from 1.2 to 1.8 volts. Detailed analyses of the circuit gain and noise are provided. In addition, the effect of circuit topology on the noise performance is discussed. The effect of 1/f noise on accuracy of the circuit is also negligible due to resetting the charge-integrating capacitor after each comparison. A prototype chip is fabricated in 0.18- μm CMOS. The circuit dissipates 15 μW with 5.5 kS/s conversion rate from a 1.5 V supply. The complete interface circuit has 14 pJ/c-s figure of merit and 7.6 effective number of bits.
14 citations
01 Dec 2008
TL;DR: To achieve high speed, the proposed A/D converter utilizes Threshold Inverter Quantization technique replacing conventional analog comparators with digital comparators, resulting in a faster digital conversion and a reduction of the analog nodes in the ADC.
Abstract: This paper presents a Resolution Adaptive Flash A/D Converter design and its performance. To achieve high speed, the proposed A/D converter utilizes Threshold Inverter Quantization technique replacing conventional analog comparators with digital comparators. The replacement results in a faster digital conversion and a reduction of the analog nodes in the ADC. The proposed ADC is a true variable resolution ADC, operates at 3-bit, 4-bit, 5-bit and 6-bit precision depending on control inputs. The proposed ADC is designed with AMS 0.35 mum CMOS technology and 3.3 V power supply voltage and a prototype chip is fabricated. Simulation results and test results are presented.
14 citations
01 Sep 2013
TL;DR: A dithering technique for linearization of VCO-based ADCs is proposed that obviates the need for power-hungry digital calibration techniques or expensive front-end loop-filters.
Abstract: A dithering technique for linearization of VCO-based ADCs is proposed The proposed technique conditions the signal to the VCO input to appear as white noise thereby eliminating spurious signal content arising out of the VCO non-linearity The technique, thus obviates the need for power-hungry digital calibration techniques or expensive front-end loop-filters A prototype implementation (in 65nm CMOS) based on the technique achieves 10-b ENOB in digitizing signals with 50MHz bandwidth consuming 82mW at an FoM of 90fJ/convstep
14 citations
TL;DR: In this amplifier-intensive architecture utilizing 36 ringamps, the 4-GS/s ADC fabricated in 16-nm CMOS achieves 62-dB SNDR and 75-dB SFDR at Nyquist, consumes 75 mW, and has a Walden figure of merit (FoM) of 18 fJ/conversion-step and a Schreier FoM of 166 dB, advancing the state of the art in direct-RF sampling ADCs by roughly an order of magnitude.
Abstract: A $4\times $ interleaved pipelined ADC for direct-RF sampling applications is presented. It leverages the performance advantages of ring amplifiers to unlock greater architectural freedom. The first pipeline stage MDAC with a “passive-hold” mode eliminates the sub-ADC sampling path and associated problems. A high-speed ringamp topology employs digital bias control, robust common-mode feedback (CMFB), and an elegant self-resetting behavior. An asynchronous, event-driven timing control system improves several aspects of performance and enables fully dynamic power consumption and modular design re-use. A general technique is presented whereby the signal-to-distortion ratio (SDR) of any amplifier in the system can be measured in the background with an analog hardware overhead of only one comparator. In this amplifier-intensive architecture utilizing 36 ringamps, the 4-GS/s ADC fabricated in 16-nm CMOS achieves 62-dB SNDR and 75-dB SFDR at Nyquist, consumes 75 mW (including input buffer), and has a Walden figure of merit (FoM) of 18 fJ/conversion-step and a Schreier FoM of 166 dB, advancing the state of the art in direct-RF sampling ADCs by roughly an order of magnitude.
14 citations
Patent•
IBM1
TL;DR: In this article, a method and apparatus for detecting and correcting double errors automatically by generating syndrome S bits from a binary word having check bits and data bits was provided, and the syndrome S themselves themselves were decoded to locate and correct single errors.
Abstract: A method and apparatus are provided for detecting and correcting double errors automatically by generating syndrome S bits from a binary word having check bits and data bits. The syndrome S bits themselves are decoded to locate and correct single errors. Wen double errors occur in the binary word, the syndrome S bits automatically operate a switching device which changes the bits of the binary word one at a time to correct one of the double errors. If one of the double errors is not corrected when a given bit is changed, this is indicated by the syndrome S bits, and the bit under test is restored as the next bit of the binary word is changed or complemented. Whenever one of the double errors is corrected by the switching device, the syndrome bits then indicate the location of the remaining single error, and the syndrome S bits are decoded to correct the second one of the double errors.
14 citations