Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

A power and area efficient 65 nm CMOS delay line ADC for on-chip voltage sensing

Abstract: This paper presents a 4-bit windowed delay line ADC implemented in 65 nm CMOS technology for VLSI dynamic voltage scaling power management applications. Good linearity is achieved in the proposed power and area efficient ADC without the use of resistors for compensation. The circuit performance was analyzed theoretically and verified experimentally. The measured DNL is within ±0.25 LSB and INL ±0.15 LSB. It occupies an area of 0.009 mm2. With a sampling rate of 4 MHz, the ADC is measured to consume a power of 14 µW with ENOB of 4.1 and voltage sensing range from 0.87 V to 1.32 V.

Logic circuit and method for carry and sum generation and method of designing such a logic circuit

Abstract: Logic circuit for generating carry or sum bit output by combining binary inputs, includes bit level carry generate and propagate function logic receiving binary inputs and generating bit level carry generate/propagate function bits for binary inputs by respectively logically AND and OR combining respective bits of binary inputs; logic generating high output if a carry is generated out of a first group of most significant bits of binary input or if carry propagate function bits for the most significant bits are all high; logic for receiving bit level carry generate and propagate function bits for binary inputs to generate high output if any of carry generate function bits for the most significant bits are high or if carry is generated out of another group of least significant bits of binary input; and logic for generating the carry or sum bit output by combining outputs of the two logics.

Modulation/demodulation method and apparatus

Abstract: In a modulation/demodulation system for an infrared data communication, a three-bit serial-to-parallel converting circuit captures an input signal in units of three bits in synchronism with an input clock, and outputs a three-bit parallel data to a decoder. This decoder converts the three-bit parallel data into a four-bit parallel data having different patterns corresponding to all different patterns of the three-bit parallel data in a one-to-one relation. In this four-bit parallel data, regardless of how the four-bit parallel data are serially arranged, the total length of the continuing “1” bits is two bits at maximum, and the total length of the continuing “0” bits is six bits at maximum. A four-bit parallel-to-serial converting circuit receives the four-bit parallel data, to serially output a serial data in synchronism with a modulation clock. Thus, the data transfer rate can be elevated in the infrared data communication.

Digital-domain calibration of split-capacitor DAC with no extra calibration DAC for a differential-type SAR ADC

Abstract: A digital-domain calibration is proposed for a split-capacitor DAC of a 0.5 V 11 bit 10 kS/s differential-type SAR ADC. The calibration improves the linearity of ADC, especially INL by +1.59/-1.71 LSB, SFDR by 19.1 dB, and SNDR by 5.0 dB (ENOB by 0.83 bits). It compensates both the mismatch among binary-weighted capacitors and the errors due to parasitic capacitance of bridge-capacitor and LSB bank. No extra calibration DAC is required in this work, because one of the two differential DAC branches is used to measure errors of the other DAC branch. Measurements on the fabricated chip with a 0.13 mm CMOS process show INL +0.78/-0.89 LSB, DNL +0.75/-0.89 LSB, SNDR 61.7 dB (ENOB 9.96 bits), and SFDR 81.8 dB at the Nyquist rate. The power consumption and FoM of analog block are 560 nW and 55 fJ/conversion-step, respectively.

Device for real-time correction of errors in data recorded on a magnetic medium

Abstract: The error-correcting device for processing data in parallel on a plurality of tracks provides two levels of correction on the basis of redundancy bits added to the transmitted data, namely bits resulting from coding in blocks of serial data on each channel by means of a shortened Fire code (200, 180), and parity bits each relating to one-half of the parallel tracks. An array of decoders delivers the data corrected on the basis of the bits resulting from the Fire code which are substituted when necessary for the data stored in a memory. When the errors in a block of one of the tracks are too long to be corrected in this manner, two parity computers associated with multiplexers permit determination of the erroneous bits.