Topic
Effective number of bits
About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.
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31 Oct 2008TL;DR: The design and wafer probe test results of a 5-bit SiGe ADC, fabricated in a 200/250 GHz fT/Fmax, SiGe BiCMOS technology, provides 5- bit analog to digital conversion with input tone frequencies up to 20 GHz and sampling clock rates up to 35 GS/s.
Abstract: The design and wafer probe test results of a 5-bit SiGe ADC are presented. The integrated circuit, fabricated in a 200/250 GHz fT/Fmax, SiGe BiCMOS technology, provides a 5-bit analog to digital conversion with input tone frequencies up to 20 GHz and sampling clock rates up to 35 GS/s. The ADC makes use of a comparator with an integrated exclusive-or function to reduce power consumption. The device also generates two half-rate interleaved outputs to ease in data capturing with laboratory equipment. An effective number of bits (ENOB) of nearly 5.0 is achieved for low frequency input tones, dropping to 4.0 at 10 GHz.
14 citations
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30 May 1978TL;DR: In this paper, an analog-to-analog converter is coupled to a successive approximation register for providing an indication of whether the value of the most significant bits is other than zero.
Abstract: An expanded analog-to-digital converter includes a first digital-to-analog converter for converting the most significant bits of digital output signal having a given number of bits to a first analog reference signal having a value that is proportional to the value of the most significant bits minus one-half the least significant bit of the digital output signal whenever the value of the most significant bits is other than zero; and a second digital-to-analog converter for converting the least significant bits of the digital output signal to a second analog reference signal. A successive approximation register successively provides the bits of a digital output signal in accordance with a comparison of an analog input signal with the sum of the analog reference signals. A logic circuit coupled to the successive approximation register for providing an indication of whether the value of the most significant bits is other than zero, causes the second analog reference signal to have a value that is proportional to the value of the least significant bits whenever the value of the most significant bits is other than zero, and a value that is proportional to the value of the least significant bits minus one-half the least significant bit of the digital output signal whenever the value of the most significant bits is zero.
14 citations
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26 May 2019TL;DR: This paper presents an energy-efficient 12-bit successive-approximation register (SAR) analog-to-digital converter (ADC) for biomedical and IoT applications and the synchronous SAR ADC operation was applied to meet the scaling of the sampling frequency for extending the battery life.
Abstract: This paper presents an energy-efficient 12-bit successive-approximation register (SAR) analog-to-digital converter (ADC) for biomedical and IoT applications. The synchronous SAR ADC operation was applied to meet the scaling of the sampling frequency for extending the battery life. The full capacitor swapping scheme was proposed to maintain both small input capacitance, better ADC linearity and SNDR. The 12-bit ADC was fabricated using a 180-nm CMOS technology. This prototype ADC consumes only 730 nW from a 0.7-V supply at 100-kS/s. With the Nyquist rate input, the measured SNDR and SFDR are 64.2 and 75 dB, respectively. The ENOB is maintained at 10.4 bits, equivalent to a figure-of-merit of 5.6 fJ/conversion-step. The sampling frequency can be scaled from 100 kHz to 1 kHz with ENOB > 10.4 bits.
14 citations
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03 Aug 2010TL;DR: The simulation results show that the proposed charge compensation technique can improve the Effective Number of Bits (ENOB) from 8.3bits to 9.6bits and differential/integral nonlinearity from 3LSB/1.65LSB to 0.45LSB / 0.74LSB respectively with only 300 uW power dissipation in the proposed charges compensation circuitry.
Abstract: A voltage feedback charge compensation technique is presented to prevent the conversion nonlinearity due to the parasitic effect of split capacitive DAC structure in successive approximation register (SAR) ADCs. The charge compensation is achieved by using an open loop amplifier that performs voltage feedback to the DAC array via a compensation capacitor, which is easy to be implemented with very low power dissipation. The technique is utilized in the design of a 10b 80MS/s SAR ADC in 65-nm CMOS technology. The simulation results show that the proposed charge compensation technique can improve the Effective Number of Bits (ENOB) from 8.3bits to 9.6bits and differential/integral nonlinearity from 3LSB/1.65LSB to 0.45LSB/0.74LSB respectively with only 300 uW power dissipation in the proposed charge compensation circuitry.
14 citations
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12 Jun 2009TL;DR: In this article, a most significant bits analog to digital converter for determining the first P bits of an N bit analog-to-digital conversion is presented. But the converter must be a digital to analog converter with a capacitive attenuator.
Abstract: A most significant bits analog to digital converter for determining a first P bits of an N bit analog to digital conversion, the most significant bits analog to digital converter comprising: a digital to analog converter a capacitive attenuator, and a switching arrangement for inhibiting action of the attenuator during sampling and enabling the attenuator during conversion.
14 citations