Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

1-GHz GaAs ADC building blocks

Abstract: GaAs ICs for high-speed, 6-b, 1G-sample/s (Gs/s) data acquisition are under development, using a low-cost conventional D-MESFET technology. First-generation sample-and-holds (S/Hs) and comparators are currently being sampled to customers. Diode-bridge and FET-switch S/Hs have been compared. Best performances have been achieved with diode-bridge switches: 1 ns and 6 bits. Comparators provide 6-b sensitivity at 1 GHz, but require offset adjustments. Second-generation analog-to-digital converter (ADC) building blocks have been made. Performances and applications of resulting circuits as well as advanced ADC design criteria are discussed, with special attention to yield. First results on a 4-b ADC are presented. >

A simple structure for noise-shaping SAR ADC in 90nm CMOS technology

Abstract: This paper presents a simple structure for error feedback based noise-shaping successive approximation register (NSSAR) analog-to-digital converter (ADC), which obviates the need for a high output swing, fast-settling and high gain Operational Transconductance Amplifier (OTA). The ADC has a simple structure and its quantization noise is extracted and transferred via a finite impulse response (FIR) filter, without any attenuation. To make a good matching, a 5-bit segmented array is utilized as a digital-to-analog converter (DAC). In this way, the required total capacitance of the ADC is reduced more than 96% compared to a 10-bit conventional SAR (CSAR) ADC. Also, due to noise-shaping property the comparator specifications are relaxed. The ADC is designed and simulated in 90 nm CMOS technology with HSPICE simulator. Simulation results show that the ADC's average power consumption is about 4.4 μW at a 0.5 V power supply. By using an oversampling ratio (OSR) of 16, the ADC achieved maximum SNDR and SFDR of 59.6 dB and 58 dB, respectively, from transient noise simulation. The figure of merit (FoM) is about 56.4 fJ/conversion-step.

Defect detection and correction via monitoring of syndromes and bit flips in decoder

Abstract: A system for reading data from a data storage device includes a channel detector configured to detect bits of digital data corresponding to the data read from the storage device, and, for each of the bits of digital data, determine a probability that each of the bits is a 0 or a 1. A decoder module is configured to generate confidence indicators associated with a first subset of the digital data. The confidence indicators include the probability, received from the channel detector, that each of the bits in the first subset of the digital data is a 0 or a 1, and/or bit flip data indicating a number of times each of the bits in the first subset of the digital data was flipped during decoding. A digital defect detection module is configured to selectively identify the first subset of the digital data as defective based on the confidence indicators.

A 8.9-ENOB 2.5-εW 150-KS/s non-binary redundant successive approximation ADC in 0.18-μm CMOS for bio-implanted devices

Abstract: A successive approximation analog-to-digital converter (SAR ADC) with a split-capacitor switching scheme implementing the generalized non-binary redundant SAR algorithm and an energy efficient level shifter is proposed for bio-implanted applications. The generalized non-binary redundant SAR algorithm removes the radix constraint in conventional non-binary redundant SAR algorithm, and the energy efficient level shifter allows optimal power supplies to be chosen independently for the analog and digital blocks. A FOM of 34.7fJ/step has been achieved.

Effects of quantization noise in parallel arrays of analog-to-digital converters

Abstract: High-speed A/D conversion can be achieved by using a parallel array of digitizers interleaved in time and in voltage Alternatively, the input analog signal can be first decomposed into several frequency bands and then have each frequency band digitized by a separate A/D converter This paper investigates the quantization noise effects in such structures, and shows that by using a filter bank before and after a parallel array of A/D converters, an increase in the effective number of bits of resolution can be obtained >