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Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.


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Journal ArticleDOI
TL;DR: A 12-bit successive approximation register (SAR) ADC based on dynamic tracking algorithm and a real-time QRS-detection algorithm are proposed that achieves FoM of 48 fJ/conversion-step at the best case.
Abstract: A 12-bit successive approximation register (SAR) ADC based on dynamic tracking algorithm and a real-time QRS-detection algorithm are proposed. The dynamic tracking algorithm features two tracking windows which are adjacent to prediction interval. This algorithm is able to track down the input signal’s variation range and automatically adjust the subrange interval and update prediction code. QRS-complex detection algorithm integrates synchronous time sequential ADC and real-time QRS-detector. The chip is fabricated in a standard 0.13 $\mu \text{m}$ CMOS process with a 0.6 V supply. Measurement results show that proposed ADC exhibits 10.72 effective number of bit (ENOB) and 79.63 dB spur-free dynamic range (SFDR) at 10k Hz sample rate given 41.5 Hz sinusoid input. The DNL and INL are bounded at −0.6/0.62 LSB and −0.67/1.43 LSBs. The ADC achieves FoM of 48 fJ/conversion-step at the best case. Also, the prototype is experimented with ECG signal input and extracts the heart beat signal successfully.

14 citations

Journal ArticleDOI
TL;DR: A novel closed-loop switched-capacitor capacitance-to-frequency converter (CFC) is presented in this article, capable of measuring from either a single-element or a differential capacitive sensor, providing ratio and ratiometric outputs, respectively.
Abstract: A novel closed-loop switched-capacitor (SC) capacitance-to-frequency converter (CFC) is presented in this article. The proposed CFC is capable of measuring from either a single-element or a differential capacitive sensor (DCS), providing ratio and ratiometric outputs, respectively. Most of the existing autobalancing schemes for capacitive sensors use the closed-loop approach but require precise sinusoidal ac excitation and provide an analog output that is sensitive to parasitic capacitances. Also, the use of voltage-controlled resistors (VCRs) in many of these schemes limits the linearity and accuracy of their output. The SC-CFC presented in this article employs a simple dc reference for excitation and gives a digital output that is insensitive to parasitic capacitances, by virtue of design. Additionally, the output is linear, irrespective of the sensor characteristic, and independent of the nominal value of the sensor. This feature, along with its compatibility with single-element and DCSs, facilitates its ease of integration with a wide range of capacitive sensors. The CFC has a one-time correction mechanism that significantly reduces the impact of component mismatch. The prototype of the proposed scheme exhibits a maximum nonlinearity error (NLE) of 0.24%, a resolution of 12.59 effective number of bits (ENOB), and a rise time of 6 ms. In addition, the proffered design is fit for integrated circuit (IC) fabrication as it employs an SC approach.

14 citations

Proceedings ArticleDOI
01 Aug 2007
TL;DR: A low power 1 V 10-bit successive approximation analog-to-digital converter (SA-ADC) is presented for biomedical applications and a charge-recycling method for switching the capacitors is used.
Abstract: A low power 1 V 10-bit successive approximation analog-to-digital converter (SA-ADC) is presented for biomedical applications. In the DAC capacitor arrays of this SA-ADC a charge-recycling method for switching the capacitors is used. Besides, a 1 V rail-to-rail input comparator with both current driven bulk technique and offset cancellation is proposed. The complete 1 V ADC implemented in TSMC 0.18 um CMOS process has a signal-to-noise ratio of 58.5 dB and its effective number of bits is 9.4 based on post-layout simulations. The entire ADC power consumption is 32.6 uW for normal signals and 29.5 uW for ECG applications.

14 citations

Patent
Masaru Yano1
30 Jan 2002
TL;DR: In this paper, a system for programming verification that intelligently reprograms failed bits without excessively stressing bit logic in the device is presented, which operates to detect bits that have failed a programming verify operation and to reprogram these bits with an adjusted programming voltage so as to obtain the desired Vt while reducing stress on the bits and achieving a narrow Vt distribution.
Abstract: System for programming verification that intelligently reprograms failed bits without excessively stressing bit logic in the device. The system operates to detect bits that have failed a programming verify operation and to reprogram these bits with an adjusted programming voltage so as to obtain the desired Vt while reducing stress on the bits and achieving a narrow Vt distribution.

14 citations

Journal ArticleDOI
16 Dec 2015-Sensors
TL;DR: This paper proposes capture modules implemented in an FPGA which are able to perform smart acquisition that filter noise and achieve high precision and a calibration technique is also proposed to improve accuracy.
Abstract: Direct sensor–digital device interfaces measure time dependent variables of simple circuits to implement analog-to-digital conversion. Field Programmable Gate Arrays (FPGAs) are devices whose hardware can be reconfigured to work in parallel. They usually do not have analog-to-digital converters, but have many general purpose I/O pins. Therefore, direct sensor-FPGA connection is a good choice in complex systems with many sensors because several capture modules can be implemented to perform parallel analog data acquisition. The possibility to work in parallel and with high frequency clock signals improves the bandwidth compared to sequential devices such as conventional microcontrollers. The price to pay is usually the resolution of measurements. This paper proposes capture modules implemented in an FPGA which are able to perform smart acquisition that filter noise and achieve high precision. A calibration technique is also proposed to improve accuracy. Resolutions of 12 effective number of bits are obtained for the reading of resistors in the range of an example piezoresistive tactile sensor.

14 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202361
2022143
202196
2020147
2019149
2018147